[EMAIL PROTECTED] wrote:
>
> I would like to make a series of statements here and appreciate
> anyone's comments as to their truth or idiocy.
Excellent questions Phil. Or is it Phillip? Questions like
this really get me going, but it's a lot of fun. Let's see
what kind of treatment we can come up with on the subject of....
PC Architecture
---------------------------
In the beginning, God created the universe with certain
fundamental quantities we call units that can be symbolized:
M = mass (kilogram)
L = length (meter)
T = time (second)
A = electric current (ampere)
K = temperature (kelvin)
And perhaps candelas, moles, radians and steradians. All the
quantities we measure today are combinations of the above fundamental
units.
mi L
speed = ---------- = -------
hour T
meters meters L
acceleration = ----------- = ---------- = ----------
sec� sec x sec T x T
and so on. A few billion years later, around 600 BC, the Greek
Philosophers found that amber, when rubbed, would collect bits
of straw. Consequently the word electron comes from the Latin
electrum and Greek elektron, meaning amber.
The movement of and attraction between electrons led to Maxwell's
equations for electromagnetism. Using his equations and derived
values like voltage and amperage gave rise to electronics in the
1800's. Contributions by Einstein, Bohr, Heisenberg and others
led to the creation of Quantum mechanics and Quantum theory, which
simply states that physical systems behave in terms of levels when
you examine them at the very-microscopic scale. They don't exhibit
a continuous range of behavior - they exhibit behavior at specific
levels. They only accept energy in specific amounts, and they
only give off energy in specific amounts.
For instance, an electron can't orbit an atom with any amount of
energy infused into the electron, it can only accept an infusion of
energy of a specific amount. If you hit an electron with just the
right amount of energy, it will absorb that energy into its movements
and move to and exist at a higher orbit - a higher energy level. If
you put in two times the exact energy, it jumps two levels.
In other words the electrons hovering around the atoms in your *blue*
jeans only absorb light that has the exact energy amount needed for that
electron to jump to the next level. In this case that exact amount of
energy is the energy contained in blue light. Green light has the wrong
energy and won't be absorbed by the electrons. But blue light is absorbed.
But now the atom is unstable, because it has more energy than what
normally makes it stable. So the electron falls back to the lower
energy level it came from, giving off the exact amount of energy it
took in. That exact amount of energy is the energy value of blue
light. Summary: the electron absorbs only blue light and reradiates
only blue light, and you see blue jeans.
That's what happens when energy states are quantized.
Electronics work in a quantized nature on macro and microscopically. On
the large scale, to simulate a number, a circuit could +5 volts to represent
a 1 and ground to represent a 0. The presence of +5 V or GND on a wire
indicates a 1 or a 0 is present. The need to control the output of ones
and zeros on a wire led to the invention of the vacuum tube. A vacuum
tube is an on-off switch. You switch it on with by sending a +5 V on a
control line and +5 V will appear on the output line.
On the microscopic level, electronic devices use quantum mechanics.
When physicists applied quantum theory to materials constructed of silicon,
arsenic, gallium, yttrium, barium, and copper oxide, that work lead to the
creation of super-miniature switches that were much better than their bulky
vacuum tubes ancestors. These new switches, called transistors, are superior
to vacuum tubes for most purposes.
The early transistors were called BJTs (Bipolar Junction Transistors) as
versus FETs (Field Effect Transistors), and they looked like this :
______,_________ +5 V
|
BJT | collector
TRANSISTOR |
__|___
base | |
______________| |
| |
|______|
\
\ emitter
\
\
The base is what you control. The emitter is where your data is. If you
hold the base at +5 V, or high, then current flows from the collector to
the emitter. Making creative connections with resistors between various
pins of a transistor is what gives positive feedback (gain) or negative
feedback. That's how you amplify a signal in your stereo.
These BJTs are no good compared to the newer FETs, of which MOSFETs are
the best variety for computer usage. MOSFETs (Metal Oxide Semiconductor
Field Effect Transistors) are superior because the "base" draws no current,
and thus offers a tremendously high impedance, i.e.. not loading down the
rest of your circuit (sucking the amps out of it).
MOSFETs are distinguished from FETs on the engineering level due to the
presence of a thin layer of Silicon Dioxide (SiO2) between the n layer of
the semiconductor and the "base" contact. This thin layer is more commonly
known by it other name, glass. It's very thin, often less than the wave-
length of visible light, but it can handle voltages across it up to 20V
with no current flowing through it.
I know, I know, get on to IDE!
Ok. So MOSFET switches are combined into miniature IC chips that perform
logic, which makes a computer capable. For instance, if a passenger door
is open AND the driver is sitting down, sound the buzzer:
Driver Door Buzzer Logic
-----------------------------
AND logic gate
______,
DOOR OPEN ____________| =
| '=___________ ALARM line
DRIVER SEATED ________| .=
|______=
If you put +5 V on DOOR OPEN and +5 V on DRIVER SEATED, then ALARM line
will go high to +5 using a cmos AND gate.
There are AND, NAND, OR, NOR, NOT, XOR, and XNOR logic chips to make
all kinds of decisions. These logic circuits are the foundation of all
computer decisions and control. They come in ON/OFF variety, and
they come in OFF/ON/NC variety, the tri-state variety.
The other fundamental component of a computer is a Flip-Flop. That's
a miniature circuit composed of a few MOSFETs that holds a value of
1 or 0 on it's output, until told to change it. That's memory.
When you group 8 flip-flops together conceptually, you are looking at
a group of eight 1's or 0's. Each flip-flop is called a bit, and a group
of bits is called a register. A group of 8 bits is a "byte."
Some groups of bits
----------------------
expressed value value
in binary in decimal in hex
smallest: 0000 0000 0 0
0000 0001 1 1
0000 0010 2 2
0000 0011 3 3
... ... ... ...
largest: 1111 1111 15 F
Group two bytes together, and you have a 16 bit register, or a "word."
Some examples in binary and their hex value underneath:
0000 0000 0000 0000
0 0
0000 0000 0000 0001
0 1
0000 0010 0000 0011
2 3
1111 1111 1111 1111
F F
Group two words together and you have a (32 bit) double word or
'dword' for short. Again that's
Label is composed of
-------- --------------
bit 1 bit
byte 8 bits
word 16 bits
dword 32 bits
Here's a picture of a bunch of words stacked
16 ________________ 0
|________________|
|________________|
|________________|
|________________|
|________________|
|________________|
When you stack a bunch of words in succession like this, you have
a picture of what RAM looked like, groups of 16 flip-flop registers,
one after the other. RAM is simply a lot of these registers. RAM
is 64 bits wide these days, not 16.
A few registers also live on the CPU, to handle temporary values.
So now that we've laid out the fundamental building blocks of a
computer, let's build one!
In the beginning.... STOP that!
Ok, in 1975, Altair made the first personal computer, the model 8800,
which was a big box of switches and lights but no LED digits at all,
and sold them to hobbyists like Steve Wozniak (one of the first phone
phreaks, but that's another thread).
http://www.hyperweb.com/altair/
By 1980, Compaq, Tandy, Apple, and a host of others were making
computers based on the Commodore 6502 processor. Others were working
on a Motorola 68008 cpu, like Sun, and NeXT.
I built my first 68008 computer from capacitors, resistors, flip-flops,
multiplexors, decoders, and the like on a breadboard in 1993. If I could
find the gif, I'd put it up. I was trained, as were many others, using
the Harvard course "The Art of Electronics" by Horowitz and Hill. A lot
of this material is gleaned from there. If you take a year of college
analog and digital electronics, there's a good chance you'll use it too.
Let's take a peek under the hood of a generic CPU so we can get the
vocabulary and concepts necessary to understand buses, cpus and PC's --
the object of object of this essay:
C P U
_________________________________________________________________
| __________ _____________ |
| | | | Arithmetic | ____________ |
| | L1 cache | | Logic | | | |
| |__________| | Unit (ALU) | | Flags | |
| |_____________| |____________| |
| |
| |
| General Purpose Registers |
| ________________ |
| _________ _____________ |________________| |
| | Program | | Instruction | |________________| |
| | Counter | | Decoder | |________________| |
| |_________| |_____________| |________________| |
| |________________| |
| |________________| |
| _________ |________________| |
| | Stack | |________________| |
| | Pointer | _____________________ |
| |_________| | | |
| | Bus Control | |
| |_____________________| |
|_________________________________________________________________|
| |
| |
| Front |
| Side |
| Bus |
\ | | /
\ /
\ /
\ /
\/
I call this a generic cpu, because all cpu's follow very similar
principles. They all do their computation on chunks of data in
registers. Here's what all those pieces do:
Instruction Decoder: Interprets the your program's instructions
that are fetched from memory and figures out what to do then.
ALU: Performs arithmetic functions like add, subtract, multiply,
and shift on groups of bits called
Registers: which hold data on the cpu temporarily.
Program Counter: Another special register that keeps track of
where in the list of program instructions the cpu is working at.
The counter usually increments by 1 after each instruction, but
it can jump (JMP) to a new instruction, skipping others.
Stack Pointer: This register holds the current position in memory
one past where the last word of data was written.
Flags: These can be like sign, zero, carry
L1 Cache: A small chunk of very quickly access memory that's
closely connected to the general purpose registers and holds
values recently fetched from main memory.
Bus Control Circuitry: Handles communication with memory and any
I/O devices.
Finally PC Bus Architecture! A simple example:
A cpu communicates with *all* other devices of a computer using a
single bus, the system bus (which is referred to nowadays as the Front
Side Bus). My simple example shows how the FSB is shared by every
device. There has to be agreement on who talks and who listens and
when to put data on the bus.
This would look something like this for:
A simple cpu, bus, and device with
8 data lines and 16 address lines
-------------------------------
cpu bus device
________ ________
| | | |
| |______________________________D0_________| |
| |______________________________D1_________| this |
| | 8 DATA lines <----> ... | device |
| |______________________________D6_________| could |
| |______________________________D7_________| be any |
| | | one of |
| | | eight |
| | | ISA |
| |_________ STROBE line ---> ______________| slots |
| | | for |
| | | example|
| | | |
| | | |
| |_______________________________A0________| or an |
| |_______________________________A1________|old IDE |
| |_______________________________A2________| drive |
| |_______________________________A3________| |
| | 16 ADDRESS lines ---> ... | |
| |______________________________A15________| or RAM |
| | | |
|________| |________|
The guts of all Data Buses are: DATA, ADDRESS, and STROBE.
Now notice the little arrows.
<-------> means bi-directional. DATA lines are bi-directional,
meaning data can move on them from cpu to device or
from device to cpu. DATA lines connect to CMOS gates
on the device. The CMOS gates must not put their
data on the DATA lines unless it's their turn. When
it's not their turn, their D0-D7 must not be held
HIGH or LOW. Rather they must be NC, i.e.. not connected,
and that's why we need tri-state CMOS gates (they can
be on/off/nc).
--------> ADDRESS lines go from CPU to devices or from cpu to ram,
one way only. Address lines are used to select where
the data goes. The address that's put on those lines
may refer to a memory address or an I/O address. Devices
have a base address assigned to them and they watch for
it. When they see their address, they take action.
Because addressing goes in one direction and all the
devices must constantly listen for their address, the
CMOS gates attached to A0-A15 can be two-state, on/off
gates.
---------> Strobe: But the devices only take action when they get
a pulse from the CPU on the strobe line.
In this simple setup, all the devices, be they RAM, modems, or
whatever, wait for the CPU to tell them when to read or write data to
the D0-D7 lines. The CPU would know when to read or write data because
the program it's running would say, "Read a number, read another number,
add them, display the result." At the time when each of these steps is
to take place, the CPU notifies the devices by putting the right address
on A0-A15 and flicks the strobe.
So _it's the program that decides on the I/O_, or Programmed I/O for
short, or PIO.
That's PIO folks. :)
Ever heard of it?
PIO mode 1 for slow IDE drives??? PIO mode 4???
Wow, now we're really learning something :) We know exactly how PIO
data transfers work. And we know the fundamentals of bus architecture.
In general, though, there are more like four strobe lines, such as READ,
WRITE, READFROMMEM, WRITETOMEM. But those are called
IOR
IOW
MEMR
MEMW
The devices react when those go from high to low on the leading
edge of the pulse, but sometimes the devices react on the trailing
edge of the pulse.
So that's what happens when the CPU decides on what to move and when.
But what about when someone hits a key on the keyboard or presses "scan"
on their scanner? The CPU wouldn't know when that's going to happen.
So more complex data bus architectures are needed.
To deal with devices wanting to communicate without waiting, there
are three methods:
Status registers
Interrupts
Direct Memory Access (DMA)
Status registers: The device sets a bit HIGH on itself and the cpu
knows to check the address where that status bit is, and the CPU polls
that status bit regularly by doing PIO on that bit of data. The bit
is cleared bye the cpu when the data is read. The drawback is that
the device still has to wait for its status register to be polled.
Interrupts: A device interrupts the flow of the CPU's instructions,
causing it to stop and execute a special set of instructions for that
device. How it works is that there are 15 interrupt lines on a PC,
called IRQ1 - IRQ15 that added to the front side bus that are connected
to the CPU's interrupt controller. To make an interrupt, a device
raises it's assigned interrupt high. This causes the CPU to stop
executing after it's next instruction. It will then save it's flags
and its current program counter location out to the RAM stack, and
jump to the device's interrupt handler routine program somewhere in
memory. The device manufacturer writes this handler program to do
what they want, like read a key from the keyboard or some data from
the disk. When done, it jumps back to where it left off, and the CPU
continues on with it's next instruction. Shared interrupts, interrupt
masks, and interrupt acknowledgment are beyond the scope of this document
(yea!).
DMA: To understand DMA and it's advantage, it's important to realize
that devices, when they want to put some data into memory (like reading
a gif image from a drive into memory), must move the data in chunks like
this:
the data *first* moves from the device into the CPU general purpose
registers (using PIO IN),
*then* the data moves from the CPU into the RAM (using PIO OUT).
That's two steps. DMA gets around this intermediate player, the cpu,
by allowing a device to send data directly to RAM. That's one step not
two. DMA can work from device to device, not just device to RAM. For
instance DMA is very useful when doing transfers from a disk to a tape.
DMA is necessary with modern devices because they would have to raise
interrupts on the �sec scale. DMA works like this: The device raises
certain "bus request" lines, which are additional lines on the bus.
The CPU gives permission to the device and then backs off from control
of the bus. The CPU lets the device set the address lines (which now
have to be bi-directional!) and lets the device set the data on D0-D7
and lets the device strobe as needed. In other words it lets the device
become the thing that controls the bus, or the thing that masters the
bus. Devices like this are called bus mastering devices.
Wow, bus mastering ide controllers!
Is there more? Sure 'nough!
Knowing all that we know now about computers and buses, let's see if
we can't draw a:
PC Architecture Conceptual Layout
-------------------------------------
_______________
| |
| C P U |
|____ ____|
| |
| |
| FSB |
| |
_______| |______
| | __________
| |_____________| |
| North Bridge ____FSB______ Memory |
| | | |
|_ ________ _| |__________|
| | | |
| | | |
AGP bus | |
| | | PCI |
Video card | Bus |
| |
_____________________| |__________________________________________
PCI Bus PCI Bus
__ ___________ _________________________ _____________ _________
| | || | | | |
| | || | | | |
__| |__ ____||_____ | | | |
| South | | EIDE Host | _______| |___ ___| |_______
| Bridge| | Controller| | PCI CardBus | | ATA-100/133 |
|__ _| |_ ___ _| | Bridge | | host |
| | | | | | |__ ________| | controller |
| | primary | | | | |__ ________|
| | IDE secondary PC Card sockets | |
| | IDE | |
| | disk drives
___| |______________
ISA Bus
____ ______________
| |
| |
___| |_____
| Logic |___ com1,2
|controllers|__ parallel
|___________|
| |
| |
keyb flop
And finally, to tie it all together, a last little bit about the
number of DATA lines, ADDRESS lines, and RAM. We've shown how computers
uses buses to communicate, and we've shown an example where data moves
on 8 DATA lines and addresses use 16 ADDRESS lines. We've also learned
that ADDRESS lines can be used to specify a place in memory. How many
possible memory registers can we enumerate in an address with 16 bits?
1 0000 0000 0000 0000
2 0000 0000 0000 0001
3 0000 0000 0000 0010
4 0000 0000 0000 0011
... ... ... ... ...
65534 1111 1111 1111 1101
65535 1111 1111 1111 1110
65536 1111 1111 1111 1111 = 2^16
So 16 ADDRESS lines can refer to 65,536 memory registers, or you can
say that 16 bit addressing can handle 65K of RAM. That's 2 to the
power of the number of address lines.
Now back to history, data bit and address bits. Wouldn't it be better
if our simple example could communicate of 16 DATA lines also, not just 8?
That would could move data twice as fast. So how was it done?
Well the Commodore 64, in 1980 was the benchmark of the industry, using
an 8/16 architecture (8 bits for DATA / 16 bits for ADDRESS) meaning that
it could talk to 64K of RAM. Back then, both Apple and Commodore came
with 64K of RAM off the shelf because DRAM was getting cheap back then.
But IBM wasn't in the game, and they wanted in!
So what do they do? They see falling ram prices and that 64K is being
sold in all the good computers. That means that need a computer capable
of dealing with more ram? Well if they used an 8/16 architecture, why
not move up to a 16/32 architecture?
32 ADDRESS lines = 2^32 registers = 4GB of registers
So 32 lines could refer to 4GB or ram. But there were no 16/32 style
CPUs in 1980, so they settled on an 16/16 processor called the 8086 made
by Intel that used all 16 bit internal registers. But they still wanted
to access more RAM. So they got tricky and used one of the 16-bit onboard
registers called a "segment" register for the addressing and shifting 4
bits to the left then adding using 20 bit arithmetic and coming up with
a 20 bit address. These 20-bits can spell out 2^20 different addresses,
i.e.. refer to 1 MB of RAM.
And remember a segment, when holding the left shift part constant, can
only span 64K (it's a 16 bit register). To cap it, IBM only let us use
10 different segments out of the 1 MB of ram, or 640K of RAM.
Damn! That's where the 640K limitation comes from!
Ok now when IBM released the PC blueprint so everybody could clone it,
that meant that the 8086 standards got set into stone. Each future CPU
version that was released had to still conform to the 8086 standards,
meaning that they newer CPU's had to deal with devices that could only
handle 16 bit addressing. That meant that newer CPUs like the 286, 386,
and 486 which would have 16/32 or larger architectures would still have
to be able to speak in good ol' 8086 mode. So they made all future CPUs
with two modes, real mode (acts like and 8086) and protected mode (acts
like whatever it is, a 16/32 or 32/32 or whatever). In order to boot
and function with whatever it old style devices it might find, a CPU
starts in real mode every time. So even today, we are stuck with real
mode, 8086 booting with only 640 KB of RAM.
Neat!
The later CPUs created a ramdisk in the other 15 MB of RAM using
ramdisk.sys. A program that needed more RAM could set a status bit that
caused the CPU to switch to protected mode. When the code snippet was
done, the CPU would require a complete reset to switch back to real mode.
Very few programs used protected mode. It was too much trouble.
To be exact, though, IBM started with an 8088, not an 8086. The 8088
was a 16/16 internally only, but external to the cpu, it only used 8
bits of DATA lines.
CPU Family Data bits / Address bits
60008 8/20
Commodore 64 8/16
8088 8/16
80286 16/24
80386 32/32
80486 32/32
Pentium 60 64/64
It took 90 days working 24/7 to make a Pentium CPU.
===================================================================
That's about it. I'm burnt :-) Now, on to your questions...
> The IDE interface is not a true disk controller, like SCSI, it is more
> like a memory mapping, with the the controller residing in the disk drive.
IDE and EIDE are registered trademark names owned by Western Digital.
Common names for these drives are now:
Now called was called
---------- ------------
ATA IDE
ATA2 EIDE
ATA-33 UDMA
ATA-66 UDMA-66
ATA-100 ATA-100
The original ATA drives were PIO devices, limited to 528 MB, and were
connected to the ISA bus!
ATA2 connected to the PCI bus, was limited to 37 GB, and could do DMA
(but they called it PIO mode 3 and PIO mode 4).
The primary and secondary ATA-33/66 channels are multitasking and
don't step on each others toes. But the MASTER and SLAVE devices on a
single channel are singletasking. Only one can talk at once. (We know
why... it's a shared bus) If you mix an ATA-66 drive and a PIO mode 4
cdrom as MASTER and SLAVE, both will run in PIO mode 4.
We've seen how the ATA host controller bridge connects to the PCI bus.
And we've seen how an ATA host controller splits itself into two channels.
These ATA host controllers split the bus into two channels and are used
to buffer the data onto the bus using tri-state data and address lines.
So your are correct in essence.
The device that actually runs each drive is also called a controller,
which is confusing, and is integrated into the circuit board of the
drive. IDE stands for Integrated Device Electronics, and the controller
is what's integrated. The MASTER device's controller is also responsible
for controlling the SLAVE on that channel.
> Either: PCMCIA is a true independent bus with its own controller
chip set.
> Or: PCMCIA is a 68 pin adaptation which must piggy back on PCI
et. al.
The pci bus is a 32 bit data bus that runs at 33 Mhz. In general,
the computer can move a 32 bit register in one clock.
If we decide to transfer only 8 bits per clock (1 byte), and there
are 33 million clocks per second, we can move:
1 byte 33 M clocks
------- x ------------ = 33 MB/s
1 clock 1 sec
If we use: 1 word/clock --------> = 66 MB/s
If we use 1 dword/clock which is
32 bits/clock, the full
capacity, that's -----> = 132 MB/s
The PC Card bridge to the PCI bus, called the CardBus bridge nowadays,
supports a 32 bit wide PC Card data bus that is capable of DMA and using
interrupts. It acts similarly to the ATA-100 bridge, but is rather
different in that it has to deal with the insertion and removal (hot
swapping) of PC Cards, card recognition, assigning interrupts, etc. The
CardBus bridge is a controller unto it's own that creates the PC Card bus
that the PC Cards plug into. So it doesn't get involved in running every
type of card, more like recognizing, and buffering. I'm new to these
devices, and that's my humble take on it so far.
> SanDisk, et all, produce a flash memory device in the PCMCIA form factor.
> This device has IDE emulation logic built in (this is true).
Roger that.
> SanDisk, et al, produce an adapter, converting the 68 pin flash
> memory to a 50 pin IDE cable (also true).
Affirmative.
> A new form factor has emerged called Compact Flash (digital cameras,
> 50 pin ) which can also be treated as an IDE drive ( also true).
> This is NOT a PCMCIA device (???)
Correct, the Compact Flash invented by SanDisk is not a PC Card device.
It is it's own incarnation with the benefits of small size, low power
draw, a sturdy 50-pin connector, and perfect emulation of PC Cards or
ATA drives. It can connect to the PC Card bus via an adapter.
> DLink, et al, are putting a 802.11b wireless card with antenna on
> Compact Flash.
Sounds interesting. Do you have a link?
> Somewhere ?? there is an effort underway to provide access point
> software on Linux for these IDE wireless cards. ??????
Yes there is. It's actually not that hard, in theory. Many modern WiFi
PC Cards are based on the Intersil Prism2, and with those you can set
them into access point mode, so to speak.
http://www.muppetlabs.com/~mikeh/linux_wap.html
Welp, you've just read one of my top 5 best followups, the result of
organic french roast and chocolate birthday cake. I hope you got as
much enjoyment out of this as I did from writing it :-)
Matthew
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