On Tue, Dec 22, 2015 at 10:44 PM, Janne Grunau <[email protected]> wrote: >> Intel's current documentation is very clear on cvtpi2ps: "This >> instruction causes a transition from x87 FPU to MMX technology >> operation". > > every tested silicon (nothing ancient or SSE only though) and the copy > of the manual from 1999 (Order Number 243191) (Pentium 3 and SSE were > intruduced 1999) disagree. The instruction reference manual from 2002 > (Order Number 245471-006) misses the comment. But that could easily be > an edit error. The comments from the end of the instruction description > were removed and the main description was extended.
Huh, that's interesting. Also note that cvtpi2ps and cvtpi2pd has different exception mechanics as well. > Since it will probably take ages to get this resolved: adding a emms > before the return of int32_to_float_fmul_scalar_sse is enough for all > x86 systems/calling conventions? That seems like to easiest, safest and most compatible way of handling it. Especially considering that CPUs with SSE2 won't even run that code path anyway. _______________________________________________ libav-devel mailing list [email protected] https://lists.libav.org/mailman/listinfo/libav-devel
