Supply some ARM signal handler code for icache-hygiene, and an ARM icache
flush function.
Signed-off-by: Steve Capper <steve.cap...@arm.com>
---
tests/icache-hygiene.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/tests/icache-hygiene.c b/tests/icache-hygiene.c
index eb64a62..c1f2f66 100644
--- a/tests/icache-hygiene.c
+++ b/tests/icache-hygiene.c
@@ -52,8 +52,10 @@ static long hpage_size;
static void cacheflush(void *p)
{
-#ifdef __powerpc__
+#if defined(__powerpc__)
asm volatile("dcbst 0,%0; sync; icbi 0,%0; isync" : : "r"(p));
+#elif defined(__arm__)
+ __clear_cache(p, p + COPY_SIZE);
#endif
}
@@ -97,7 +99,7 @@ static void sig_handler(int signum, siginfo_t *si, void *uc)
}
FAIL("SIGILL somewhere unexpected");
}
-#elif defined(__i386__) || defined(__x86_64__)
+#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__)
/* On x86, zero bytes form a valid instruction:
* add %al,(%eax) (i386)
* or add %al,(%rax) (x86_64)
@@ -121,10 +123,12 @@ static void sig_handler(int signum, siginfo_t *si, void
*uc)
FAIL("SIGBUS somewhere unexpected");
}
if (signum == SIGSEGV) {
-#ifdef __x86_64__
+#if defined(__x86_64__)
void *pc = (void *)((ucontext_t
*)uc)->uc_mcontext.gregs[REG_RIP];
-#else
+#elif defined(__i386__)
void *pc = (void *)((ucontext_t
*)uc)->uc_mcontext.gregs[REG_EIP];
+#elif defined(__arm__)
+ void *pc = (void *)((ucontext_t
*)uc)->uc_mcontext.fault_address;
#endif
verbose_printf("SIGSEGV at %p, PC=%p (sig_expected=%p)\n",
--
1.8.0.2
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