On Thu, Feb 21, 2013 at 10:39:08PM +0000, David Gibson wrote:
> On Thu, Feb 21, 2013 at 03:57:38PM +0000, Steve Capper wrote:
> > Supply some ARM signal handler code for icache-hygiene, and an ARM icache
> > flush function.
> >
> > Signed-off-by: Steve Capper <steve.cap...@arm.com>
> > ---
> > tests/icache-hygiene.c | 12 ++++++++----
> > 1 file changed, 8 insertions(+), 4 deletions(-)
> >
> > diff --git a/tests/icache-hygiene.c b/tests/icache-hygiene.c
> > index eb64a62..c1f2f66 100644
> > --- a/tests/icache-hygiene.c
> > +++ b/tests/icache-hygiene.c
> > @@ -52,8 +52,10 @@ static long hpage_size;
> >
> > static void cacheflush(void *p)
> > {
> > -#ifdef __powerpc__
> > +#if defined(__powerpc__)
> > asm volatile("dcbst 0,%0; sync; icbi 0,%0; isync" : : "r"(p));
> > +#elif defined(__arm__)
> > + __clear_cache(p, p + COPY_SIZE);
> > #endif
> > }
> >
> > @@ -97,7 +99,7 @@ static void sig_handler(int signum, siginfo_t *si, void
> > *uc)
> > }
> > FAIL("SIGILL somewhere unexpected");
> > }
> > -#elif defined(__i386__) || defined(__x86_64__)
> > +#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__)
> > /* On x86, zero bytes form a valid instruction:
> > * add %al,(%eax) (i386)
> > * or add %al,(%rax) (x86_64)
>
> It would be nice to update this comment for the arm case. Basically
> what exactly is going on when executing a page of zeroes - on x86 we
> execute right through it harmlessly, then get a SEGV when we run off
> the end. Is that the same for arm? Could the 0-bits instruction have
> any side effects?
>
Thank you David, having put a comment in there for ARM, it is apparent
that we should only expect a SIGBUS and not a SIGSEGV so I've also
de-activated the SIGSEGV handler in the revised patch (which I'm about
to send in a separate email).
Thanks,
--
Steve
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