I think there is a mistake in scb.h-- /* SHP: System Handler Priority Registers */ /* Note: 12 8bit registers */ #define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) #define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1) #define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) #define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
I think these should be defined as-- MMIO32(SCB_BASE + 0x18) MMIO32(SCB_BASE + 0x1C) etc, I ran across the problem with setting the priority of the SYSTICK interrupt priority. The first of the following instructions works correctly, the second does not. *(u32*)0xE000ED20 |= (SYSTICK_PRIORITY_SE << 24); SCB_SHPR3 |= (SYSTICK_PRIORITY_SE << 24); Both load the correct address into the R3, then load R2 with the register. However, the first of the above "or's" in the priority correctly, the second simply stores without or'ing in the shifted priority. No gcc warnings either. I'm using the earlier svn based libopenstm32, but I downloaded the latest 'cm3 and I find it is still the same. Maybe someone could fix this. I'm not sure how to go about do it. Don PS: This resulted in an extremely vexing bug where the situation required the systick interrupt to be at a lower priority than an adc register watchdog interrupt. The result was an infrequent glitch that only occurred under certain circumstances. The systick priority, of course, was defaulting to level 0. ------------------------------------------------------------------------------ See everything from the browser to the database with AppDynamics Get end-to-end visibility with application monitoring from AppDynamics Isolate bottlenecks and diagnose root cause in seconds. Start your free trial of AppDynamics Pro today! http://pubads.g.doubleclick.net/gampad/clk?id=48808831&iu=/4140/ostg.clktrk _______________________________________________ libopencm3-devel mailing list libopencm3-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/libopencm3-devel
