Hi *,
I've got a NUCLEO-F401RE board[1] from ST featuring a STM32F401RE MCU[2].
The MCU does support a maximum system clock of 84MHz and the board does
not provide an external clock source for the MCU, so one needs to use
the HSI as PLL source.
So I added a function rcc_clock_setup_in_hsi_out_84mhz() to the STM32F4
rcc code of libopencm3. See the attached patch below.
It would be grate if the code could be added upstream. :)
Further more I'm currently porting the stm32f4-discovery examples to the
stm32f401re-nucleo (which is straight forward, all ready got miniblink,
button and mandel running). If you are interested I'd be happy to share
the code, too...
Many thanks for providing this grate free library!
cheers
sascha
[1] http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260000
[2]
http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00102166.pdf
--
Sascha Wilde : xedit? Das sieht zwar wie vi aus als könne es nix, aber im
: Gegensatz zu vi kann es wirklich nix und nix ist noch geschönt!
: (Michael Core in dafc)
diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h
index 0d094f7..14592ca 100644
--- a/include/libopencm3/stm32/f4/rcc.h
+++ b/include/libopencm3/stm32/f4/rcc.h
@@ -778,6 +778,7 @@ void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp,
uint32_t pllq);
uint32_t rcc_system_clock_source(void);
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock);
+void rcc_clock_setup_in_hsi_out_84mhz(void);
END_DECLS
diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c
index d862691..b01b342 100644
--- a/lib/stm32/f4/rcc.c
+++ b/lib/stm32/f4/rcc.c
@@ -534,6 +534,45 @@ void rcc_clock_setup_hse_3v3(const clock_scale_t *clock)
rcc_osc_off(HSI);
}
+void rcc_clock_setup_in_hsi_out_84mhz(void)
+{
+ /* Enable internal high-speed oscillator. */
+ rcc_osc_on(HSI);
+ rcc_wait_for_osc_ready(HSI);
+
+ /* Select HSI as SYSCLK source. */
+ rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
+
+ /* no power saving */
+ pwr_set_vos_scale(SCALE2);
+
+ /*
+ * Set prescalers for AHB, ADC, ABP1, ABP2.
+ * Do this before touching the PLL (TODO: why?).
+ */
+ rcc_set_hpre(RCC_CFGR_HPRE_DIV_NONE);
+ rcc_set_ppre1(RCC_CFGR_PPRE_DIV_2);
+ rcc_set_ppre2(RCC_CFGR_PPRE_DIV_NONE);
+
+ rcc_set_main_pll_hsi(16, 336, 4, 7);
+
+ /* Enable PLL oscillator and wait for it to stabilize. */
+ rcc_osc_on(PLL);
+ rcc_wait_for_osc_ready(PLL);
+
+ /* Configure flash settings. */
+ flash_set_ws(FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS);
+
+ /* Select PLL as SYSCLK source. */
+ rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
+
+ /* Wait for PLL clock to be selected. */
+ rcc_wait_for_sysclk_status(PLL);
+
+ /* Set the peripheral clock frequencies used. */
+ rcc_ppre1_frequency = 42000000;
+ rcc_ppre2_frequency = 84000000;
+}
/**@}*/
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