2 AHB cycles are generally essentially one instruction so a delay is
somewhat pointless, there are 4 AHB cycles consumed when returning from the
call to rcc_periph_clock_enable(). This limitation would be hit if you were
to pipeline the clock enable and the first register write in sequence so
something like
RCC_AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
GPIO_MODSETR(GPIOA) |= 0x33;
This becomes an issue when you have enable and access instructions in the
mini-instruction cache of the F7 I suspect.
--Chuck
On Sun, Mar 12, 2017 at 7:33 PM, Matthew Lai <m...@matthewlai.ca> wrote:
> Noticed this while going through the stm32f7 reference manual (RM0385),
> and thought it's interesting:
>
> Each peripheral clock can be enabled by the xxxxEN bit of the RCC_AHBxENR
> or RCC_APBxENRy registers. When the peripheral clock is not active, the
> peripheral registers read or write accesses are not supported. The
> peripheral enable bit has a synchronization mechanism to create a glitch
> free clock for the peripheral. After the enable bit is set, there is a 2
> peripheral clock cycles delay before the clock being active.
>
> Just after enabling the clock for a peripheral, software must wait for a 2
> peripheral clock cycles delay before accessing the peripheral registers.
>
> This is not mentioned in the stm32f42x reference manual for example.
> However, there's something similar on the errata sheet (and for stm32l1 as
> well) [1][2]:
>
> A delay between an RCC peripheral clock enable and the effective
> peripheral enabling should be taken into account in order to manage the
> peripheral read/write to registers. This delay depends on the peripheral's
> mapping:
>
> • If the peripheral is mapped on AHB: the delay should be equal to 2 AHB
> cycles.
>
> • If the peripheral is mapped on APB: the delay should be equal to 1 +
> (AHB/APB prescaler) cycles.
>
> Should we add the delays to rcc_periph_clock_enable() and
> rcc_peripheral_enable_clock()?
>
> Matthew
>
> [1]: http://www.st.com/content/ccc/resource/technical/document/
> errata_sheet/68/8c/cb/af/de/48/40/17/DM00097022.pdf/files/
> DM00097022.pdf/jcr:content/translations/en.DM00097022.pdf
>
> [2]: http://www.st.com/content/ccc/resource/technical/document/
> errata_sheet/38/e6/37/64/08/38/45/67/DM00068628.pdf/files/
> DM00068628.pdf/jcr:content/translations/en.DM00068628.pdf
>
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