In at least the stm32/f4 version of rcc_wait_for_sysclk_status()
the check is looking at the read/write control bits which set the
clock source (SW1,SW0) instead of the status bits (SWS1,SWS0).
I think this is the correction:
diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c
index a9441e8..2c34869 100644
--- a/lib/stm32/f4/rcc.c
+++ b/lib/stm32/f4/rcc.c
@@ -414,13 +414,16 @@ void rcc_wait_for_sysclk_status(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
- while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
+ while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & 0x3)
+ != RCC_CFGR_SWS_PLL);
break;
case RCC_HSE:
- while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
+ while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & 0x3)
+ != RCC_CFGR_SWS_HSE);
break;
case RCC_HSI:
- while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
+ while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & 0x3)
+ != RCC_CFGR_SWS_HSI);
break;
default:
/* Shouldn't be reached. */
If a MASK value was defined then the 0x03 should be replaced with that.
The header file is inconsistant about having MASK values or not.
(Please let me know if you prefer this in some other form etc.)
Don Reid
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