Chris Chiappa wrote:
> <griffon>KeyserSoze-pts/3[1]~$ uptime
> 10:54am up 15 days, 13:50, 8 users, load average: 2.15, 2.08, 2.03
> This is with one of the QQ beta bioses. I still don't trust the board
> though, and would never recommend it (or any other ABit board for that
> matter; their behavior with this has been inexcusable). I still
> occasionally get APIC warnings, even when not overclocked. In the past if
> I've even moderately overclocked, the board has becom way too unstable.
As you say, this is your opinion and I respect it even if I disagree.
When I bought my BP6, I did not expect it to be rock-stable. Intel
says the Celeron has not be certified for SMP, and I believe them.
Abit has warnings all over their manual that SMP is for experimental
purposes. From all this I infer the BP6 might be instable. IMHO,
anyone who uses one without extensive stability testing in a setting
where crashes have high consequences is foolhardy. BP6 or SMP aren't
"slap together" systems. Adjust your expectations.
So I wrote `burnP6` and later `burnBX` specifically to test for
stability. I have obtained 10+ days uptime, but I don't run my
BP6 continuously because the fans make more noise than I'd like
and my power [Houston] is too unreliable. [My wife has the UPS]
But I have no unexplained crashes at 2 * 5.5 * 97 MHz . I will
get 2-3 burnBX data errors per day at 98 MHz which would probably
crash the machine in a few weeks under X.
If you are worried about filesystem corruption, I'd suggest you
try FreeBSD with SoftUpdates. I've pulled the plug on 4 kernel
compiles (about 50 seconds in on 70 seconds total). In all cases,
the reboot fsck was trivial, and for 3 only `make` finished up fine,
just losing 25 seconds data. For the 4th, I had to do a `make clean`
then `make` worked normally. Outstanding FS performance! Enabling
SoftUpdates is a bit of a rigamarole.
Anyway, Intel themselves have had plenty of trouble with PPGA SMP.
Note they needed a major stepping cB0 to make the P!!! PPGA SMP work
stably. Then have a look at the P3 PPGA SMP design guide (Feb 00).
Abit didn't have this when they designed the BP6 ~18 months ago.
PPGA SMP is tougher than the ungainly SECC because there are no
decoupling caps on the PPGA [unlike the P5mmx ppga]. So the current
slews are _very_ high: 240 A/us vs 20 for the SECC. The P3 SMP DG
is very insistant about decoupling cap placement.
Leading edge is bleeding edge. I don't blame Abit, but too I wonder
if they couldn't have handled the v1.1 issue better. Alot would depend
on knowing what they knew, and when. AFAIK, the board has been out
of production for 6+ months. It isn't the hot board in their shop.
-- Robert author `cpuburn` http://users.ev1.net/~redelm
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