Zdenek Kabelac wrote:
> Anyway I'll try to use binary halving to find some more reasonable
> value - but maybe other people with the same problem could try
> this by themself.
>
> (value 120 = 0x78 seems to be to low - 0x98 to high)
The PCI latency timer was intended to be calculated by teh BIOS.
PCI devices declare "I have a buffer for 4 microseconds" and another
device may say "I have a buffer for 10 microseconds".
The BIOS should then calculate that there are 3 busmastering devices
on the bus, and that to satisfy the 4 microseconds restriction no
device can hold the bus for longer than 2 microseconds. Thus the
latency timer should be set to 66 PCI clock cycles.
However, this calculation is not quite as simple as I pretend it
is. Thus in the beginning the BIOS writers would just have a parameter
in the setup screesn that was labelled "PCI latency timer". Nobody
knew how/when to change them. So everybody stuck with the default.
(I had a board that said: "78 is optimal. Your warranty is void if you
change it")
Then the latency requirement values were not really used anyway, so
some vendors made mistakes in the values that were programmed in those
registers. Next you know those values are unreliable, so that you HAVE
to let the user decide. Or the BIOS. So nowadays the BIOS usually
takes a wild guess ("32 sounds about right") and puts that in the
latency timer register.
It is not a value that will make a world of difference between two
values. It is also not something that is "portable" from one computer
to the next, unless they are COMPLETELY identical.
Roger.
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