On 8/20/2018 6:39 PM, Maciej W. Rozycki wrote:
On Mon, 20 Aug 2018, Sinan Kaya wrote:
That is that the caller must not
assume that writes issued by `writeX' calls will be observed in order on
the external bus or specifically by the device addressed.
Where do you see it?
Right in the first paragraph of io_ordering.txt, and then further
demonstrated by the examples provided ("In the case above, the device may
receive newval2 before it receives newval, which could cause problems.").
I interpret that two writeX() need to be observed in order with respect
to each other without requiring an explicit barrier. Same goes for reads.
Nope, only if `readX' is in between.
Likewise see memory-barriers.txt throughout concerning `mmiowb' (which is
an obviously lighter weight barrier compared to `readX').
Here is a better reference from memory-barriers.txt
(*) readX(), writeX():
Whether these are guaranteed to be fully ordered and uncombined with
respect to each other on the issuing CPU depends on the
characteristics
defined for the memory window through which they're accessing. On
later
i386 architecture machines, for example, this is controlled by way
of the
MTRR registers.
Ordinarily, these will be guaranteed to be fully ordered and
uncombined,
provided they're not accessing a prefetchable device.
Maciej
