On Mon, 20 Aug 2018, Sinan Kaya wrote:
> > That is that the caller must not
> > assume that writes issued by `writeX' calls will be observed in order on
> > the external bus or specifically by the device addressed.
>
> Where do you see it?
Right in the first paragraph of io_ordering.txt, and then further
demonstrated by the examples provided ("In the case above, the device may
receive newval2 before it receives newval, which could cause problems.").
> I interpret that two writeX() need to be observed in order with respect
> to each other without requiring an explicit barrier. Same goes for reads.
Nope, only if `readX' is in between.
Likewise see memory-barriers.txt throughout concerning `mmiowb' (which is
an obviously lighter weight barrier compared to `readX').
Maciej
