Mark Hull-Richter wrote:
>
> Chance Reschke wrote:
> >
> > A question: I've heard that in the 21264/EV6 SMP design all interrupts
> > are handled by CPU0. Is this true? Can anyone report on the impact
> > this has on the behavior of these systems in Beowulf configurations or
> > anywhere else with lots of network or disk I/O?
> >
> Yes, as far as I know that's true. It was anticipated that this would
On the DP264 motherboard with the Tsunami chipset that is -not- true.
The Tsunami chipset has separate processor 0 and processor 1 interrupt
registers (interrupt requests, interrupt masks, etc.) So the hardware
is capable of delivering individual interrupts to specific processors.
However, the software must have a mechanism for supporting such a
hardware design. On the dual processor intel platforms the same rules
apply so I -assume- Linux has a mechanism for designating interrupts to
processors. But, I don't know for sure. Assignment of interrupts to
specific processors (or to multiple processors) is either limited by
software or hardware. In the case of the DP264, the hardware is not the
limiting factor.
I have looked at the code in a pre 2.2 version and found that only one
host bridge was supported. I'd be interested in sharing a solution I
employed to get both host bridges on the DP264 working. My solution
applied to a proprietary O/S (can you guess which one? ;-) but it's
fair for me to share the general strategy employed.
-- Randy
