On Tuesday, March 22, 2005 9:44 am, James Bottomley wrote: > As an aside, the main ordering problem it prevents is the SMP one where > two CPUs do writes into the PCI domain that they order with spinlocks. > Even though, temporally, the writes are sequenced leaving the CPUs, the > altix PCI domain can still re-order them if the mmiowb() isn't present > (so it sounds like it's really a smp_mmiowb()...)
Correct. And it's necessary because spin_unlock* don't do any I/O ordering by default (in fact they're only one way memory barriers on alpha and ia64 iirc). Jesse
