Linus Torvalds writes: > So the rules from the PC side (and like it or not, they end up being > what all the drivers are tested with) are: > > - regular stores are ordered by write barriers
I thought regular stores were always ordered anyway? > - PIO stores are always synchronous By synchronous, do you mean ordered with respect to all other accesses (regular memory, MMIO, prefetchable MMIO, PIO)? In other words, if I store a value in regular memory, then do an outb() to a device, and the device does a DMA read to the location I just stored to, is the device guaranteed to see the value I just stored (assuming no other later store to the location)? > - MMIO stores are ordered by IO semantics > - PCI ordering must be honored: > * write combining is only allowed on PCI memory resources > that are marked prefetchable. If your host bridge does write > combining in general, it's not a "host bridge", it's a "host > disaster". Presumably the host bridge doesn't know what sort of PCI resource is mapped at a given address, so that information (whether the resource is prefetchable) must come from the CPU, which would get it from the TLB entry or an MTRR entry - is that right? Or is there some gentleman's agreement between the host bridge and the BIOS that certain address ranges are only used for certain types of PCI memory resources? > * for others, writes can always be posted, but they cannot > be re-ordered wrt either reads or writes to that device > (ie a read will always be fully synchronizing) > - io_wmb must be honored What ordering is there between stores to regular memory and stores to non-prefetchable MMIO? If a store to regular memory can be performed before a store to MMIO, does a wmb() suffice to enforce an ordering, or do you have to use mmiowb()? Do PCs ever use write-through caching on prefetchable MMIO resources? Thanks, Paul. - To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
