Alan Cox <[EMAIL PROTECTED]> wrote: > [For information on bus mastering DMA and coherency please read ....] > > sincee have a doc on this
Documentation/pci.txt? > The use of volatile generates poorer code and hides the serialization in > type declarations that may be far from the code. I'm not sure what you mean by that. > Is this true of IA-64 ?? Are you referring to non-temporal loads and stores? > > +There are some more advanced barriering functions: > > "barriering" ... ick, barrier. Picky:-) > Should clarify local ordering v SMP ordering for locks implied here. Do you mean explain what each sort of lock does? > > + (*) inX(), outX(): > > + > > + These are intended to talk to legacy i386 hardware using an alternate > > bus > > + addressing mode. They are synchronous as far as the x86 CPUs are > > Not really true. Lots of PCI devices use them. Need to talk about "I/O space" Which bit is not really true? David - To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
