From: Paul Mackerras <[EMAIL PROTECTED]> Date: Thu, 9 Mar 2006 09:01:57 +1100
> On PPC machines, the PTE has a bit called G (for Guarded) which > indicates that the memory mapped by it has side effects. It prevents > the CPU from doing speculative accesses (i.e. the CPU can't send out a > load from the page until it knows for sure that the program will get > to that instruction) and from prefetching from the page. > > The kernel sets G=1 on MMIO and PIO pages in general, as you would > expect, although you can get G=0 mappings for framebuffers etc. if you > ask specifically for that. Sparc64 has a similar PTE bit called "E" for "side-Effect". And we also do the same thing as powerpc for framebuffers. Note that on sparc64 in our asm/io.h PIO/MMIO accessor macros we use physical addresses, so we don't have to map anything in ioremap(), and use a special address space identifier on the loads and stores that indicates "E" behavior is desired. - To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
