Philip Blundell said:
> This patch is now on ftp.netwinder.org. It should fix a few problems that
> people had with the previous patch. Fingers crossed, NWFPE-as-module really
> should work this time and I added the LEDs bits that got missed before
> around - basically you can now ask them to turn a particular colour. BTW,
> it would be nice if someone with an EBSA-285 could try this and see whether
> the LEDs seem to do the right thing.
Would you mind discussing/forwarding your changes and bug fixes to the relevent
maintainers at some point, rather than just overruling them snatching the maintainence
from them? I find this extremely discourtious. (and you wonder why I jump down your
throat from time to time).
> The floppy-DMA thing that I posted here the other day is now included. If it
> eats your disks I'd like to hear about it. And, uh, that's about it.
Have you tested it in the highest resolution? Although I haven't checked yet,
from the calculations I did on Thursday night, there is only about 1us every 20us
(20us is about the period between each floppy FIQ) *worst case* to allow the
foreground task to run (incuding the execution of the actual FIQ routine.
A single floppy FIQ cycle occurs about every 20us, and *MUST* be loaded within
this time or else floppy corruption occurs. What I'm not sure of is the latency
that can be allowed between the floppy requesting data and the data actually being
presented. I would imagine that this is more stringent than 20us.
Given that a single floppy FIQ cycle occurs every 20us,
- each video transfer consists of a 4 word DMA. At the highest video resolution
this occurs every 1.778us, and lasts 1.2us. In a single FIQ cycle, the video
transfer occurs 11.25 times, which gives a total bus usage of 13.5us.
- the cursor DMA consists of a 4 word DMA. This occurs every 31us. Hence it will
more than likely occur once every FIQ cycle and lasts 1.2us.
- sound DMA consists of a 4 word DMA, which at 20kHz occurs every 50us. It will
take around 1.2us.
- a podule access takes 1.2us for one cycle. A 4 register LDM or STM would take
around 3us.
- this takes out about 18.9us worst case every 20us and does not include the
time the ARM takes to synchronise with the FIQ request, enter the FIQ routine,
process the FIQ and return from it.
Hence I still don't believe that shaving an extra couple of cycles off the FIQ
will give enough time to disable and enable FIQs, which is your main reason for
implementing this change.
NOTE that if the video FIFO settings in VIDC are not programmed correctly, even
with the FIQ code as is, you *will* get undetectable corruption of floppies when
you write to them (the disk controller does not appear to flag underruns as an
error).
--
Russell King ([EMAIL PROTECTED])
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