Philip Blundell writes:
> guidelines in the MAINTAINERS file, they explicitly suggest making patches
> available for testing before bothering the maintainer.
I'm sorry - I can't find this in the Maintainers file. Could you please
give me a line number?
> >Have you tested it in the highest resolution?
>
> No. If necessary I'd be happy to do what RISC OS appears to and turn off
> video DMA in such modes during floppy access. (And since in the
> highest-bandwidth modes the video DMA consumes over half the available bus
> bandwidth it will be pretty hard to get any work done in such a mode anyway.)
Oh well, maybe we ought to ensure that nothing above 320x256 works for anyone.
Then we'll have lots of bandwidth to play with.
I don't think that mode 31 (which is what those figures were determined from)
is that bad.
> >Hence I still don't believe that shaving an extra couple of cycles off the FIQ
> >will give enough time to disable and enable FIQs, which is your main reason
> >for implementing this change.
>
> Incidentally, remember that the ARM3 is of course cached and so it isn't
> impacted as badly by bus latencies as naive calculations might show. And,
> although there is indeed all this DMA going on in the background it happens in
> many small chunks (after any of which the ARM can potentially get on the bus),
> not in one large uninterruptible lump.
Cache or no cache, the floppy DMA still has to move data, which will require
the bus. I don't think that the cache will have much effect on the timings.
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