Paul Koning said:
> >>>>> "Philip" == Philip Blundell <[EMAIL PROTECTED]> writes:
>
> >> This doesnt help you in general. Having the ring buffer uncached
> >> on a lance is the wrong solution (tm) for most platforms. Its
> >> better to flush the page out of cache and push it to memory when
> >> writing. That gets you things like burst writes.
>
> Philip> The idea for cached memory was for descriptor lists and
> Philip> things that you touch frequently but usually only a single
> Philip> word at a time. For those it seems better to have an
> Philip> uncached area than push it out of the cache all the time.
> Philip> Burst writes aren't a big deal if you're only transferring
> Philip> one word, and a single-word uncached read is actually faster
> Philip> than a cache line fill.
>
> Philip> For packet buffers and the like I agree with you.
>
> I'll second that.
However, there is a good reason why it's preferable to have the packet
buffer cached on the StrongARM - the StrongARM core switches between
a high speed clock and the bus clock. If you're doing several sequential
reads or writes, you really want the cache to be on. Otherwise the
StrongARM will switch from high to bus, back to high clock for each and
every access.
This incurs extra synchronisation delays etc, so it's not a case of
'minimal performance impact'.
It really depends on the size of the structure you're dealing with though.
--
Russell King ([EMAIL PROTECTED])
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