In the last mail Philip Blundell said:
> In message <[EMAIL PROTECTED]>, Russell King writes:
> >Philip Blundell said:
> >> > 1: ldrbt r6,[r6],#0
> >>
> >> Technically the results are UNPREDICTABLE if the two registers are the same.
> >
> >This is not illegal, nor unpredictable. The documentation says that a
> >post indexed ldr instruction must not have rd the same as rn, except in
> >one case where it is permitted. The above is an example of the exact
> >case when it is allowed.
>
> Where is this documented? The ARM says of LDRBT simply:
>
> Notes
> Register Rn:
> Specifies the base register used by <post_indexed_addressing_mode>.
>
> Operand restrictions:
> If the same register is specified for Rd and Rn the results are
> UNPREDICTABLE.
>
> This is on page 3-46.
It would seem sane for what Russell writes to be true, as I did find some
documentation of the T flag, and it says it only applies for post indexed
addressing (presumably there are 2 bits to encode 4 states:
pre indexed, pre indexed with writeback, post indexed, post indexed with
address translation) hence post index of 0 is otherwise meaningless.
However, I'm no expert, and even with -O1 can't get an inflatable kernel
(Phil predicted correctly that -O0 doesn't inline functions, hence I got >
1024 lines of link errors)
Nick
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