On Sat, 24 Apr 1999, Alan Cox wrote:
> > The StrongARM has a broken SWP implementation which means there is no
> > test-and-set instruction which is atomic to (cachable) memory. This makes
> > it somewhat difficult to make an SMP implementation. I was wondering
> > though... how about having an ELF section where all the spinlocks are
> > placed which is relocated into a non-cached region of memory? Or are
> > spinlocks part of structs these days?
>
> The strong arm has both the lock bugs and the cache flush bugs. The
> combination would make SMP suck badly I suspect
What are these bugs and where are they outlined? Also what chips
are effected (ie SA-110, SA-1100, SA-1110?)? Are the fixes in newer
steppings?
Cheers Adam
>
> Collecting locks into an ELF section would be fun as some are dynamically
> allocated - but since the field in the struct could notionally be a
> pointer to an object elsewhere not impossible
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