On Sun, 2006-23-04 at 14:54 +1200, Michal Ludvig wrote: > Did you check lspci? The GigE port is reported to sit on 32bit/66MHz PCI
Ok, so it is as you describe above. > Not yet, but stay tuned. However with your CPUs it will never be=20 > possible anyway - if they're the same as on my DP310 (family 6, model 9, = > > stepping 10, see /proc/cpuinfo) they don't support HW hashing, only=20 > encryption. > Same info as you. Heres how one of the CPU looks like: ------- processor : 1 vendor_id : CentaurHauls cpu family : 6 model : 9 model name : VIA Nehemiah stepping : 10 cpu MHz : 997.304 cache size : 64 KB fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 1 wp : yes flags : fpu vme de pse tsc msr cx8 apic sep mtrr pge cmov pat mmx fxsr sse rng rng_en ace ace_en bogomips : 1994.06 ------ > Anyway - the early DP310 boards were shipped with a buggy BIOS that > disabled CPU pipeline. This could be reconfigured by clearing bit 1 of > MSR 0x1143. See http://www.logix.cz/michal/devel/viadp310msr/ for a > simple program that does it for me. > I have downloaded this and it doesnt seem like i have that problem. --- debopolis:~# /root/viadp310msr-1.0/viadp310msr -p CPU0 pipeline length: 12 CPU1 pipeline length: 12 debopolis:~# --- I am going to try and make pipeline = 1 and see what the effect is on processing. I am recompiling the kernel turning on EHCI to see if that problem goes away once i turn things on in the BIOS. BTW, kernel compile takes forever on this thing .. cheers, jamal - To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
