This patch modifies the result handling logic to continue handling
results when the completed requests counter is full and not showing the
actual number of requests to handle.

Suggested-by: Ofer Heifetz <of...@marvell.com>
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
 drivers/crypto/inside-secure/safexcel.c | 15 ++++++++++++---
 drivers/crypto/inside-secure/safexcel.h |  2 ++
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/crypto/inside-secure/safexcel.c 
b/drivers/crypto/inside-secure/safexcel.c
index 36c9a72c47b1..8042922b4ed8 100644
--- a/drivers/crypto/inside-secure/safexcel.c
+++ b/drivers/crypto/inside-secure/safexcel.c
@@ -600,12 +600,15 @@ static inline void 
safexcel_handle_result_descriptor(struct safexcel_crypto_priv
 {
        struct safexcel_request *sreq;
        struct safexcel_context *ctx;
-       int ret, i, nreq, ndesc = 0, tot_descs = 0, done;
+       int ret, i, nreq, ndesc, tot_descs, done;
        bool should_complete;
 
+handle_results:
+       tot_descs = 0;
+
        nreq = readl(priv->base + EIP197_HIA_RDR(ring) + 
EIP197_HIA_xDR_PROC_COUNT);
-       nreq >>= 24;
-       nreq &= GENMASK(6, 0);
+       nreq >>= EIP197_xDR_PROC_xD_PKT_OFFSET;
+       nreq &= EIP197_xDR_PROC_xD_PKT_MASK;
        if (!nreq)
                goto requests_left;
 
@@ -642,6 +645,12 @@ static inline void 
safexcel_handle_result_descriptor(struct safexcel_crypto_priv
                       priv->base + EIP197_HIA_RDR(ring) + 
EIP197_HIA_xDR_PROC_COUNT);
        }
 
+       /* If the number of requests overflowed the counter, try to proceed more
+        * requests.
+        */
+       if (nreq == EIP197_xDR_PROC_xD_PKT_MASK)
+               goto handle_results;
+
 requests_left:
        spin_lock_bh(&priv->ring[ring].egress_lock);
 
diff --git a/drivers/crypto/inside-secure/safexcel.h 
b/drivers/crypto/inside-secure/safexcel.h
index 2a0ab6ce716a..0c47e792192d 100644
--- a/drivers/crypto/inside-secure/safexcel.h
+++ b/drivers/crypto/inside-secure/safexcel.h
@@ -117,6 +117,8 @@
 #define EIP197_xDR_PREP_CLR_COUNT              BIT(31)
 
 /* EIP197_HIA_xDR_PROC_COUNT */
+#define EIP197_xDR_PROC_xD_PKT_OFFSET          24
+#define EIP197_xDR_PROC_xD_PKT_MASK            GENMASK(6, 0)
 #define EIP197_xDR_PROC_xD_COUNT(n)            ((n) << 2)
 #define EIP197_xDR_PROC_xD_PKT(n)              ((n) << 24)
 #define EIP197_xDR_PROC_CLR_COUNT              BIT(31)
-- 
2.14.3

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