[PATCH v15 8/9] crypto: caam: cleanup CONFIG_64BIT ifdefs when using io{read|write}64

[Logan Gunthorpe]

Clean up the extra ifdefs which defined the wr_reg64 and rd_reg64
functions in non-64bit cases in favour of the new common
io-64-nonatomic-lo-hi header.

To be consistent with CAAM engine HW spec: in case of 64-bit registers,
irrespective of device endianness, the lower address should be read from
/ written to first, followed by the upper address. Indeed the I/O
accessors in CAAM driver currently don't follow the spec, however this
is a good opportunity to fix the code.

Signed-off-by: Logan Gunthorpe <log...@deltatee.com>
Reviewed-by: Horia Geantă <horia.gea...@nxp.com>
Reviewed-by: Andy Shevchenko <andy.shevche...@gmail.com>
Cc: Dan Douglass <dan.dougl...@nxp.com>
Cc: Herbert Xu <herb...@gondor.apana.org.au>
Cc: "David S. Miller" <da...@davemloft.net>
---
 drivers/crypto/caam/regs.h | 30 +++---------------------------
 1 file changed, 3 insertions(+), 27 deletions(-)

diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index fee363865d88..f887b371040f 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -10,7 +10,7 @@
 
 #include <linux/types.h>
 #include <linux/bitops.h>
-#include <linux/io.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
 
 /*
  * Architecture-specific register access methods
@@ -136,10 +136,9 @@ static inline void clrsetbits_32(void __iomem *reg, u32 
clear, u32 set)
  *    base + 0x0000 : least-significant 32 bits
  *    base + 0x0004 : most-significant 32 bits
  */
-#ifdef CONFIG_64BIT
 static inline void wr_reg64(void __iomem *reg, u64 data)
 {
-       if (caam_little_end)
+       if (!caam_imx && caam_little_end)
                iowrite64(data, reg);
        else
                iowrite64be(data, reg);
@@ -147,35 +146,12 @@ static inline void wr_reg64(void __iomem *reg, u64 data)
 
 static inline u64 rd_reg64(void __iomem *reg)
 {
-       if (caam_little_end)
+       if (!caam_imx && caam_little_end)
                return ioread64(reg);
        else
                return ioread64be(reg);
 }
 
-#else /* CONFIG_64BIT */
-static inline void wr_reg64(void __iomem *reg, u64 data)
-{
-       if (!caam_imx && caam_little_end) {
-               wr_reg32((u32 __iomem *)(reg) + 1, data >> 32);
-               wr_reg32((u32 __iomem *)(reg), data);
-       } else {
-               wr_reg32((u32 __iomem *)(reg), data >> 32);
-               wr_reg32((u32 __iomem *)(reg) + 1, data);
-       }
-}
-
-static inline u64 rd_reg64(void __iomem *reg)
-{
-       if (!caam_imx && caam_little_end)
-               return ((u64)rd_reg32((u32 __iomem *)(reg) + 1) << 32 |
-                       (u64)rd_reg32((u32 __iomem *)(reg)));
-
-       return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
-               (u64)rd_reg32((u32 __iomem *)(reg) + 1));
-}
-#endif /* CONFIG_64BIT  */
-
 static inline u64 cpu_to_caam_dma64(dma_addr_t value)
 {
        if (caam_imx)
-- 
2.11.0