On 4/16/2019 7:27 PM, Horia Geantă wrote: > GCM detection logic has to change for two reasons: > -some CAAM instantiations with Era < 10, even though they have AES LP, > they now support GCM mode > -Era 10 upwards, there is a dedicated bit in AESA_VERSION[AESA_MISC] > field for GCM support > > For Era 9 and earlier, all AES accelerator versions support GCM, > except for AES LP (CHAVID_LS[AESVID]=3) with revision CRNR[AESRN] < 8. > > For Era 10 and later, bit 9 of the AESA_VERSION register should be used > to detect GCM support in AES accelerator. > > Note: caam/qi and caam/qi2 are drivers for QI (Queue Interface), which > is used in DPAA-based SoCs; for now, we rely on CAAM having an AES HP > and this AES accelerator having support for GCM. > > Signed-off-by: Horia Geantă <[email protected]> Reviewed-by: Iuliana Prodan <[email protected]>
Thanks, Iulia
