On 05.01.2026 09:23, Michael S. Tsirkin wrote: > Document DMA_ATTR_CPU_CACHE_CLEAN as implemented in the > previous patch. > > Signed-off-by: Michael S. Tsirkin <[email protected]>
Acked-by: Marek Szyprowski <[email protected]> > --- > Documentation/core-api/dma-attributes.rst | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/Documentation/core-api/dma-attributes.rst > b/Documentation/core-api/dma-attributes.rst > index 0bdc2be65e57..1d7bfad73b1c 100644 > --- a/Documentation/core-api/dma-attributes.rst > +++ b/Documentation/core-api/dma-attributes.rst > @@ -148,3 +148,12 @@ DMA_ATTR_MMIO is appropriate. > For architectures that require cache flushing for DMA coherence > DMA_ATTR_MMIO will not perform any cache flushing. The address > provided must never be mapped cacheable into the CPU. > + > +DMA_ATTR_CPU_CACHE_CLEAN > +------------------------ > + > +This attribute indicates the CPU will not dirty any cacheline overlapping > this > +DMA_FROM_DEVICE/DMA_BIDIRECTIONAL buffer while it is mapped. This allows > +multiple small buffers to safely share a cacheline without risk of data > +corruption, suppressing DMA debug warnings about overlapping mappings. > +All mappings sharing a cacheline should have this attribute. Best regards -- Marek Szyprowski, PhD Samsung R&D Institute Poland
