On Thu, May 15, 2025 at 05:58:41AM +0000, Tian, Kevin wrote: > > From: Nicolin Chen <nicol...@nvidia.com> > > Sent: Friday, May 9, 2025 11:03 AM > > > > Add IOMMUFD_OBJ_HW_QUEUE with an iommufd_hw_queue structure, > > representing > > a HW-accelerated queue type of IOMMU's physical queue that can be passed > > through to a user space VM for direct hardware control, such as: > > - NVIDIA's Virtual Command Queue > > - AMD vIOMMU's Command Buffer, Event Log Buffer, and PPR Log Buffer > > > > Introduce an allocator iommufd_hw_queue_alloc(). And add a pair of > > viommu > > ops for iommufd to forward user space ioctls to IOMMU drivers. > > > > Given that the first user of this HW QUEUE (tegra241-cmdqv) will need to > > ensure the queue memory to be physically contiguous, add a flag property > > in iommufd_viommu_ops and > > IOMMUFD_VIOMMU_FLAG_HW_QUEUE_READS_PA to allow > > driver to flag it so that the core will validate the physical pages of a > > given guest queue. > > 'READS' is confusing here. What about xxx_CONTIG_PAS?
Sure. > > + * @hw_queue_alloc: Allocate a HW QUEUE object for a HW-accelerated > > queue given > > + * the @type (must be defined in > > include/uapi/linux/iommufd.h) > > + * for the @viommu. @index carries the logical HW QUEUE > > ID per > > + * @viommu in a guest VM, for a multi-queue case; @addr > > carries > > + * the guest physical base address of the queue memory; > > s/@addr/@base_addr/ > > Reviewed-by: Kevin Tian <kevin.t...@intel.com> Thanks! Nicolin
