This series was automatically blocked by Gmail due to too many recipients, so I resent it twice, causing the emails to appear discontinuous. I apologize for any inconvenience this may have caused to the reviewer.
Best regards, Xu Lu On Mon, Oct 20, 2025 at 12:21 PM Xu Lu <[email protected]> wrote: > > This patch adds support for the Zalasr ISA extension, which supplies the > real load acquire/store release instructions. > > The specification can be found here: > https://github.com/riscv/riscv-zalasr/blob/main/chapter2.adoc > > This patch seires has been tested with ltp on Qemu with Brensan's zalasr > support patch[1]. > > Some false positive spacing error happens during patch checking. Thus I > CCed maintainers of checkpatch.pl as well. > > [1] > https://lore.kernel.org/all/CAGPSXwJEdtqW=nx71oufZp64nK6tK=0rytvecz4f-gfvcox...@mail.gmail.com/ > > v4: > - Apply acquire/release semantics to arch_atomic operations. Thanks > to Andrea. > > v3: > - Apply acquire/release semantics to arch_xchg/arch_cmpxchg operations > so as to ensure FENCE.TSO ordering between operations which precede the > UNLOCK+LOCK sequence and operations which follow the sequence. Thanks > to Andrea. > - Support hwprobe of Zalasr. > - Allow Zalasr extensions for Guest/VM. > > v2: > - Adjust the order of Zalasr and Zalrsc in dt-bindings. Thanks to > Conor. > > Xu Lu (10): > riscv: Add ISA extension parsing for Zalasr > dt-bindings: riscv: Add Zalasr ISA extension description > riscv: hwprobe: Export Zalasr extension > riscv: Introduce Zalasr instructions > riscv: Apply Zalasr to smp_load_acquire/smp_store_release > riscv: Apply acquire/release semantics to arch_xchg/arch_cmpxchg > operations > riscv: Apply acquire/release semantics to arch_atomic operations > riscv: Remove arch specific __atomic_acquire/release_fence > RISC-V: KVM: Allow Zalasr extensions for Guest/VM > RISC-V: KVM: selftests: Add Zalasr extensions to get-reg-list test > > Documentation/arch/riscv/hwprobe.rst | 5 +- > .../devicetree/bindings/riscv/extensions.yaml | 5 + > arch/riscv/include/asm/atomic.h | 70 ++++++++- > arch/riscv/include/asm/barrier.h | 91 +++++++++-- > arch/riscv/include/asm/cmpxchg.h | 144 +++++++++--------- > arch/riscv/include/asm/fence.h | 4 - > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/asm/insn-def.h | 79 ++++++++++ > arch/riscv/include/uapi/asm/hwprobe.h | 1 + > arch/riscv/include/uapi/asm/kvm.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > arch/riscv/kernel/sys_hwprobe.c | 1 + > arch/riscv/kvm/vcpu_onereg.c | 2 + > .../selftests/kvm/riscv/get-reg-list.c | 4 + > 14 files changed, 314 insertions(+), 95 deletions(-) > > -- > 2.20.1 >
