On Mon, Oct 20, 2025 at 12:21 PM Xu Lu <[email protected]> wrote: > > Introduce l{b|h|w|d}.{aq|aqrl} and s{b|h|w|d}.{rl|aqrl} instruction > encodings. > > Signed-off-by: Xu Lu <[email protected]> > --- > arch/riscv/include/asm/insn-def.h | 79 +++++++++++++++++++++++++++++++ > 1 file changed, 79 insertions(+) > > diff --git a/arch/riscv/include/asm/insn-def.h > b/arch/riscv/include/asm/insn-def.h > index d5adbaec1d010..3fec7e66ce50f 100644 > --- a/arch/riscv/include/asm/insn-def.h > +++ b/arch/riscv/include/asm/insn-def.h > @@ -179,6 +179,7 @@ > #define RV___RS1(v) __RV_REG(v) > #define RV___RS2(v) __RV_REG(v) > > +#define RV_OPCODE_AMO RV_OPCODE(47) > #define RV_OPCODE_MISC_MEM RV_OPCODE(15) > #define RV_OPCODE_OP_IMM RV_OPCODE(19) > #define RV_OPCODE_SYSTEM RV_OPCODE(115) > @@ -208,6 +209,84 @@ > __ASM_STR(.error "hlv.d requires 64-bit support") > #endif > > +#define LB_AQ(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(26), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define LB_AQRL(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(27), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define LH_AQ(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(26), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define LH_AQRL(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(27), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define LW_AQ(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(26), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define LW_AQRL(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(27), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define SB_RL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(29), \ > + __RD(0), RS1(addr), RS2(src)) > + > +#define SB_AQRL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(31), \ > + __RD(0), RS1(addr), RS2(src)) > + > +#define SH_RL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(29), \ > + __RD(0), RS1(addr), RS2(src)) > + > +#define SH_AQRL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(31), \ > + __RD(0), RS1(addr), RS2(src)) > + > +#define SW_RL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(29), \ > + __RD(0), RS1(addr), RS2(src)) > + > +#define SW_AQRL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(31), \ > + __RD(0), RS1(addr), RS2(src)) > + > +#ifdef CONFIG_64BIT > +#define LD_AQ(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(26), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define LD_AQRL(dest, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(27), \ > + RD(dest), RS1(addr), __RS2(0)) > + > +#define SD_RL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(29), \ > + __RD(0), RS1(addr), RS2(src)) > + > +#define SD_AQRL(src, addr) \ > + INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(31), \ > + __RD(0), RS1(addr), RS2(src)) > +#else > +#define LD_AQ(dest, addr) \ > + __ASM_STR(.error "ld.aq requires 64-bit support") > + > +#define LD_AQRL(dest, addr) \ > + __ASM_STR(.error "ld.aqrl requires 64-bit support") > + > +#define SD_RL(dest, addr) \ > + __ASM_STR(.error "sd.rl requires 64-bit support") > + > +#define SD_AQRL(dest, addr) \ > + __ASM_STR(.error "sd.aqrl requires 64-bit support") > +#endif > + > #define SINVAL_VMA(vaddr, asid) \ > INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(11), \ > __RD(0), RS1(vaddr), RS2(asid)) > -- > 2.20.1 > I didn't find problem.
Reviewed-by: Guo Ren <[email protected]> -- Best Regards Guo Ren
