On Mon, Nov 30, 2015 at 03:51:00PM +0100, Alexander Sverdlin wrote:
> I2C controller used in Keystone SoC has an undocumented peculiarity which
> results in SDA-SCL margins being dependent on module clock. Driving high
> capacity bus near its limits can result in STOP condition sometimes being
> understood as REPEATED-START by slaves (or NACK instead of ACK, etc...).
> Driving the module with higher clocks increases the margin between SDA and SCL
> transitions, making the operations with higher bus rates more robust. 
> Therefore,
> target the module clock to 12MHz instead of 7MHz, still staying within
> the specification limits.
> 
> Before the change STOP timing looked like this on 400kHz:
> 

Applied to for-current, thanks!

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