Add ability to setup hw breakpoints using REGSET use the
__riscv_hwdebug_state structure to configure breakpoints.
Signed-off-by: Jesse Taube <je...@rivosinc.com>
---
RFC -> V1:
- New commit
V1 -> V2:
- No change
---
arch/riscv/kernel/ptrace.c | 59 ++++++++++++++++++++++++++++++++++
include/uapi/linux/elf.h | 2 ++
tools/include/uapi/linux/elf.h | 1 +
3 files changed, 62 insertions(+)
diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index e097e6a61910..fbd0097ec168 100644
--- a/arch/riscv/kernel/ptrace.c
+++ b/arch/riscv/kernel/ptrace.c
@@ -33,6 +33,9 @@ enum riscv_regset {
#ifdef CONFIG_RISCV_ISA_SUPM
REGSET_TAGGED_ADDR_CTRL,
#endif
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+ REGSET_HW_BREAK
+#endif
};
static int riscv_gpr_get(struct task_struct *target,
@@ -280,7 +283,53 @@ static long ptrace_sethbpregs(struct task_struct *child,
unsigned long idx,
return -EFAULT;
return ptrace_hbp_set(child, idx, &state);
+}
+static int hw_break_set(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ const void *kbuf, const void __user *ubuf)
+{
+ struct __riscv_hwdebug_state state;
+ int ret, idx, offset, limit;
+
+ idx = offset = 0;
+ limit = regset->n * regset->size;
+ while (count && offset < limit) {
+ if (count < sizeof(state))
+ return -EINVAL;
+
+ ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &state,
+ offset, offset + sizeof(state));
+ if (ret)
+ return ret;
+ ret = ptrace_hbp_set(target, idx, &state);
+ if (ret)
+ return ret;
+ offset += sizeof(state);
+ idx++;
+ }
+
+ return 0;
+}
+
+static int hw_break_get(struct task_struct *target,
+ const struct user_regset *regset,
+ struct membuf to)
+{
+ int ret, idx = 0;
+ struct __riscv_hwdebug_state state;
+
+ while (to.left) {
+ ret = ptrace_hbp_get(target, idx, &state);
+ if (ret)
+ return ret;
+
+ membuf_write(&to, &state, sizeof(state));
+ idx++;
+ }
+
+ return 0;
}
#endif
@@ -324,6 +373,16 @@ static const struct user_regset riscv_user_regset[] = {
.set = tagged_addr_ctrl_set,
},
#endif
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+ [REGSET_HW_BREAK] = {
+ .core_note_type = NT_RISCV_HW_BREAK,
+ .n = sizeof(struct __riscv_hwdebug_state) / sizeof(unsigned
long),
+ .size = sizeof(unsigned long),
+ .align = sizeof(unsigned long),
+ .regset_get = hw_break_get,
+ .set = hw_break_set,
+ },
+#endif
};
static const struct user_regset_view riscv_user_native_view = {
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index 819ded2d39de..7a32073e0d68 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -545,6 +545,8 @@ typedef struct elf64_shdr {
#define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */
#define NN_RISCV_TAGGED_ADDR_CTRL "LINUX"
#define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address
control (prctl()) */
+#define NN_RISCV_HW_BREAK "LINUX"
+#define NT_RISCV_HW_BREAK 0x903 /* RISC-V hardware breakpoint registers
*/
#define NN_LOONGARCH_CPUCFG "LINUX"
#define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */
#define NN_LOONGARCH_CSR "LINUX"
diff --git a/tools/include/uapi/linux/elf.h b/tools/include/uapi/linux/elf.h
index 5834b83d7f9a..b5f35df1de7a 100644
--- a/tools/include/uapi/linux/elf.h
+++ b/tools/include/uapi/linux/elf.h
@@ -460,6 +460,7 @@ typedef struct elf64_shdr {
#define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers
*/
#define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */
#define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address
control (prctl()) */
+#define NT_RISCV_HW_BREAK 0x903 /* RISC-V hardware breakpoint registers
*/
#define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */
#define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status
registers */
#define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension
registers */
--
2.43.0
