On Thu, Jul 09, 2026 at 12:12:33PM +0530, Shubham Patil wrote: > From: Manikanta Guntupalli <[email protected]> > > Add an I3C master driver and maintainers fragment for the AMD I3C bus > controller. > > The driver currently supports the I3C bus operating in SDR mode, > with features including Dynamic Address Assignment, private data > transfers, and CCC transfers in both broadcast and direct modes. It > also supports operation in I2C mode. > > The controller's data FIFOs are accessed big-endian; the driver performs > this conversion locally using ioread32be()/iowrite32be() with the > helpers, so it does not depend on any core FIFO-endianness helpers. > > Signed-off-by: Manikanta Guntupalli <[email protected]> > Co-developed-by: Shubhrajyoti Datta <[email protected]> > Signed-off-by: Shubhrajyoti Datta <[email protected]> > Co-developed-by: Shubham Patil <[email protected]> > Signed-off-by: Shubham Patil <[email protected]> > ---
Reviewed-by: Frank Li <[email protected]>
