Title: [6874] branches/2009R1/arch/blackfin: Fix bug[5287] Don't flush cache at address in L1 SRAM region.
- Revision
- 6874
- Author
- sonicz
- Date
- 2009-06-30 03:48:13 -0500 (Tue, 30 Jun 2009)
Log Message
Fix bug[5287] Don't flush cache at address in L1 SRAM region.
L1 instruction SRAM is not cachable. Executing Flush, flushinv or iflush
at this address region on bf533 v0.3 triggers double fault exception.
Although no double fault on other bfin chips, it is safe not to do it.
Modified Paths
Diff
Modified: branches/2009R1/arch/blackfin/Kconfig (6873 => 6874)
--- branches/2009R1/arch/blackfin/Kconfig 2009-06-30 06:31:14 UTC (rev 6873)
+++ branches/2009R1/arch/blackfin/Kconfig 2009-06-30 08:48:13 UTC (rev 6874)
@@ -961,21 +961,19 @@
endchoice
+config BFIN_L2_DCACHE
+ depends on (BF54x || BF561) && !SMP
+ bool "Enable L2 DCACHE"
choice
prompt "L2 SRAM cache policy"
- depends on (BF54x || BF561)
- default BFIN_L2_WT
+ depends on BFIN_L2_DCACHE
+ default BFIN_L2_WB
config BFIN_L2_WB
bool "Write back"
- depends on !SMP
config BFIN_L2_WT
bool "Write through"
- depends on !SMP
-config BFIN_L2_NOT_CACHED
- bool "Not cached"
-
endchoice
config MPU
Modified: branches/2009R1/arch/blackfin/configs/BF548-EZKIT_defconfig (6873 => 6874)
--- branches/2009R1/arch/blackfin/configs/BF548-EZKIT_defconfig 2009-06-30 06:31:14 UTC (rev 6873)
+++ branches/2009R1/arch/blackfin/configs/BF548-EZKIT_defconfig 2009-06-30 08:48:13 UTC (rev 6874)
@@ -371,9 +371,9 @@
# CONFIG_BFIN_ICACHE_LOCK is not set
CONFIG_BFIN_WB=y
# CONFIG_BFIN_WT is not set
+CONFIG_BFIN_L2_DCACHE=y
CONFIG_BFIN_L2_WB=y
# CONFIG_BFIN_L2_WT is not set
-# CONFIG_BFIN_L2_NOT_CACHED is not set
# CONFIG_MPU is not set
#
Modified: branches/2009R1/arch/blackfin/configs/BF561-EZKIT_defconfig (6873 => 6874)
--- branches/2009R1/arch/blackfin/configs/BF561-EZKIT_defconfig 2009-06-30 06:31:14 UTC (rev 6873)
+++ branches/2009R1/arch/blackfin/configs/BF561-EZKIT_defconfig 2009-06-30 08:48:13 UTC (rev 6874)
@@ -336,9 +336,9 @@
# CONFIG_BFIN_ICACHE_LOCK is not set
CONFIG_BFIN_WB=y
# CONFIG_BFIN_WT is not set
+CONFIG_BFIN_L2_DCACHE=y
CONFIG_BFIN_L2_WB=y
# CONFIG_BFIN_L2_WT is not set
-# CONFIG_BFIN_L2_NOT_CACHED is not set
# CONFIG_MPU is not set
#
Modified: branches/2009R1/arch/blackfin/include/asm/cacheflush.h (6873 => 6874)
--- branches/2009R1/arch/blackfin/include/asm/cacheflush.h 2009-06-30 06:31:14 UTC (rev 6873)
+++ branches/2009R1/arch/blackfin/include/asm/cacheflush.h 2009-06-30 08:48:13 UTC (rev 6874)
@@ -55,9 +55,15 @@
static inline void flush_icache_range(unsigned start, unsigned end)
{
#if defined(CONFIG_BFIN_WB)
- blackfin_dcache_flush_range(start, end);
+ if (start >= 0x1000 && end <= physical_mem_end)
+ blackfin_dcache_flush_range(start, end);
#endif
+#if defined(CONFIG_BFIN_L2_WB)
+ if (start >= L2_START && end <= L2_START + L2_LENGTH)
+ blackfin_dcache_flush_range(start, end);
+#endif
+
/* Make sure all write buffers in the data side of the core
* are flushed before trying to invalidate the icache. This
* needs to be after the data flush and before the icache
@@ -67,9 +73,13 @@
* the pipeline.
*/
SSYNC();
+
#if defined(CONFIG_BFIN_ICACHE)
- blackfin_icache_flush_range(start, end);
- flush_icache_range_others(start, end);
+ if ((start >= 0x1000 && end <= physical_mem_end) || (L2_LENGTH
+ && start >= L2_START && end <= L2_START + L2_LENGTH)) {
+ blackfin_icache_flush_range(start, end);
+ flush_icache_range_others(start, end);
+ }
#endif
}
@@ -107,7 +117,7 @@
addr >= _ramend && addr < physical_mem_end)
return 1;
-#ifndef CONFIG_BFIN_L2_NOT_CACHED
+#ifdef CONFIG_BFIN_L2_DCACHE
if (addr >= L2_START && addr < L2_START + L2_LENGTH)
return 1;
#endif
Modified: branches/2009R1/arch/blackfin/include/asm/cplb.h (6873 => 6874)
--- branches/2009R1/arch/blackfin/include/asm/cplb.h 2009-06-30 06:31:14 UTC (rev 6873)
+++ branches/2009R1/arch/blackfin/include/asm/cplb.h 2009-06-30 08:48:13 UTC (rev 6874)
@@ -68,14 +68,14 @@
#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
#define L2_IMEMORY (SDRAM_IGENERIC)
-# if defined(CONFIG_BFIN_L2_WB)
-# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON)
-# elif defined(CONFIG_BFIN_L2_WT)
-# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
-# elif defined(CONFIG_BFIN_L2_NOT_CACHED)
+# if defined(CONFIG_BFIN_L2_DCACHE)
+# if defined(CONFIG_BFIN_L2_WB)
+# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON)
+# elif defined(CONFIG_BFIN_L2_WT)
+# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
+# endif
+# else
# define L2_DMEMORY (CPLB_COMMON)
-# else
-# define L2_DMEMORY (0)
# endif
#endif /* CONFIG_SMP */
Modified: branches/2009R1/arch/blackfin/mach-common/arch_checks.c (6873 => 6874)
--- branches/2009R1/arch/blackfin/mach-common/arch_checks.c 2009-06-30 06:31:14 UTC (rev 6873)
+++ branches/2009R1/arch/blackfin/mach-common/arch_checks.c 2009-06-30 08:48:13 UTC (rev 6874)
@@ -74,7 +74,7 @@
/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */
#if ANOMALY_05000220 && \
- ((defined(CONFIG_BFIN_WB) && defined(CONFIG_BFIN_L2_NOT_CACHED)) || \
+ ((defined(CONFIG_BFIN_WB) && !defined(CONFIG_BFIN_L2_DCACHED)) || \
(!defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_L2_WB)))
# error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB.
#endif
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