Title: [6875] branches/2009R1/arch/blackfin: Bug[#5278] More L2 data cache options.
- Revision
- 6875
- Author
- sonicz
- Date
- 2009-06-30 04:38:43 -0500 (Tue, 30 Jun 2009)
Log Message
Bug[#5278] More L2 data cache options.
Modified Paths
Diff
Modified: branches/2009R1/arch/blackfin/include/asm/cacheflush.h (6874 => 6875)
--- branches/2009R1/arch/blackfin/include/asm/cacheflush.h 2009-06-30 08:48:13 UTC (rev 6874)
+++ branches/2009R1/arch/blackfin/include/asm/cacheflush.h 2009-06-30 09:38:43 UTC (rev 6875)
@@ -90,12 +90,12 @@
#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
-#if defined(CONFIG_BFIN_DCACHE)
+#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_L2_DCACHE)
# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end))
#else
# define invalidate_dcache_range(start,end) do { } while (0)
#endif
-#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB)
+#if defined(CONFIG_BFIN_L2_WB) && defined(CONFIG_BFIN_WB)
# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
#else
Modified: branches/2009R1/arch/blackfin/kernel/cplb-nompu/cacheinit.c (6874 => 6875)
--- branches/2009R1/arch/blackfin/kernel/cplb-nompu/cacheinit.c 2009-06-30 08:48:13 UTC (rev 6874)
+++ branches/2009R1/arch/blackfin/kernel/cplb-nompu/cacheinit.c 2009-06-30 09:38:43 UTC (rev 6875)
@@ -42,7 +42,7 @@
}
#endif
-#if defined(CONFIG_BFIN_DCACHE)
+#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_L2_DCACHE)
void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
{
unsigned long ctrl;
Modified: branches/2009R1/arch/blackfin/kernel/setup.c (6874 => 6875)
--- branches/2009R1/arch/blackfin/kernel/setup.c 2009-06-30 08:48:13 UTC (rev 6874)
+++ branches/2009R1/arch/blackfin/kernel/setup.c 2009-06-30 09:38:43 UTC (rev 6875)
@@ -83,7 +83,7 @@
static int early_init_clkin_hz(char *buf);
-#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
+#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_L2_DCACHE)
void __init generate_cplb_tables(void)
{
unsigned int cpu;
@@ -101,7 +101,7 @@
bfin_icache_init(icplb_tbl[cpu]);
#endif
-#ifdef CONFIG_BFIN_DCACHE
+#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_L2_DCACHE)
bfin_dcache_init(dcplb_tbl[cpu]);
#endif
@@ -123,6 +123,15 @@
# endif
"\n", cpu);
#endif
+#ifdef CONFIG_BFIN_L2_DCACHE
+ printk(KERN_INFO "Data Cache (L2 SRAM) Enabled"
+# if defined CONFIG_BFIN_WB
+ " (write-back)"
+# elif defined CONFIG_BFIN_WT
+ " (write-through)"
+# endif
+ "\n");
+#endif
}
void __cpuinit bfin_setup_cpudata(unsigned int cpu)
@@ -137,7 +146,7 @@
void __init bfin_cache_init(void)
{
-#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
+#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_L2_DCACHE)
generate_cplb_tables();
#endif
bfin_setup_caches(0);
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