this fault asserted when coreb starting, I don't know why link to
.l1.test section will perform
differently with 0x200 offset, it theoretically is same.
fault log:
U-Boot 2008.10-svn2131 (ADI-2009R1.1-rc1) (Dec 2 2009 - 17:36:38)
CPU: ADSP bf561-0.3 (Detected Rev: 0.5) (bypass boot)
Board: ADI BF561 EZ-Kit Lite board
Support: http://blackfin.uclinux.org/
Clock: VCO: 600 MHz, Core: 600 MHz, System: 100 MHz
RAM: 64 MB
Flash: 8 MB
In: serial
Out: serial
Err: serial
Net: MAC: 00:E0:22:FE:BA:25
Hit any key to stop autoboot: 0
Using MAC Address 00:E0:22:FE:BA:25
TFTP from server 10.99.29.111; our IP address is 10.99.29.108
Filename 'uImage'.
Load address: 0x1000000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
#################################################################
done
Bytes transferred = 4756354 (489382 hex)
## Booting kernel from Legacy Image at 01000000 ...
Image Name: bf561-2.6.34.6-ADI-2010R1-pre-sv
Image Type: Blackfin Linux Kernel Image (gzip compressed)
Data Size: 4756290 Bytes = 4.5 MB
Load Address: 00001000
Entry Point: 001a4bb0
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
Starting Kernel at = 001a4bb0
Linux version 2.6.34.6-ADI-2010R1-pre-svn9121 (ste...@debiansteven)
(gcc version 4.1.2 (ADI svn)) #218 SMP Mon Sep 6 11:26:33 CST 2010
register early platform devices
bootconsole [early_shadow0] enabled
bootconsole [early_BFuart0] enabled
early printk enabled on early_BFuart0
Board Memory: 64MB
Kernel Managed Memory: 64MB
Memory map:
fixedcode = 0x00000400-0x00000490
text = 0x00001000-0x0011aeb8
rodata = 0x0011aec0-0x0017610c
bss = 0x00177000-0x00188ec0
data = 0x00188ec0-0x0019a000
stack = 0x00198000-0x0019a000
init = 0x0019a000-0x0094a000
available = 0x0094a000-0x03f00000
DMA Zone = 0x03f00000-0x04000000
Hardware Trace Active and Enabled
Boot Mode: 0
Blackfin support (C) 2004-2010 Analog Devices, Inc.
Compiled for ADSP-BF561 Rev 0.5
Blackfin Linux support by http://blackfin.uclinux.org/
Processor Speed: 600 MHz core clock and 100 MHz System Clock
NOMPU: setting up cplb tables
NOMPU: setting up cplb tables
Instruction Cache Enabled for CPU0
External memory: cacheable in instruction cache
L2 SRAM : uncacheable in instruction cache
Data Cache Enabled for CPU0
External memory: cacheable (write-through) in data cache
L2 SRAM : uncacheable in data cache
PERCPU: Embedded 6 pages/cpu @009cf000 s3776 r8192 d12608 u65536
pcpu-alloc: s3776 r8192 d12608 u65536 alloc=16*4096
pcpu-alloc: [0] 0 [0] 1
Built 1 zonelists in Zone order, mobility grouping off. Total pages: 16002
Kernel command line: root=/dev/mtdblock0 rw clkin_hz=30000000
earlyprintk=serial,uart0,57600 console=ttyBF0,57600
ip=10.99.29.108:10.99.29.111:192.168.0.1:255.255.255.0:bf561-ezkit:eth0:off
PID hash table entries: 256 (order: -2, 1024 bytes)
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory available: 54372k/65536k RAM, (7872k init code, 1127k kernel
code, 509k data, 1024k dma, 632k reserved)
Hierarchical RCU implementation.
NR_IRQS:153
Configuring Blackfin Priority Driven Interrupts
console [ttyBF0] enabled, bootconsole disabled
console [ttyBF0] enabled, bootconsole disabled
Calibrating delay loop... 1187.84 BogoMIPS (lpj=2375680)
Mount-cache hash table entries: 512
CoreB bootstrap code to SRAM ff600000 via DMA.
Booting Core B.
Source : <0x0000d2b6> { _end_lock_coherent + 0x20 } JUMP.S
8 Target : <0x0000d296> { _end_lock_coherent + 0x0 }
Source : <0x0000d340> { ___raw_spin_unlock_asm + 0x10 } CALL pcrel
9 Target : <0x0000d338> { ___raw_spin_unlock_asm + 0x8 }
Source : <0x0000d138> { _get_core_lock + 0x40 } RTS
10 Target : <0x0000d11c> { _get_core_lock + 0x24 }
Source : <0x0000d10c> { _get_core_lock + 0x14 } IF CC JUMP pcrel
11 Target : <0x0000d107> { _get_core_lock + 0xf }
Source : <0x0000d11a> { _get_core_lock + 0x22 } JUMP.S
12 Target : <0x0000d0f8> { _get_core_lock + 0x0 }
Source : <0x0000d334> { ___raw_spin_unlock_asm + 0x4 } JUMP.L
13 Target : <0x0000d330> { ___raw_spin_unlock_asm + 0x0 }
Source : <0x0001a96a> { _acquire_console_semaphore_for_printk +
0x26 } JUMP.L
14 Target : <0x0001a950> { _acquire_console_semaphore_for_printk + 0xc }
Source : <0x0001a942> { _try_acquire_console_sem + 0x52 } RTS
15 Target : <0x0001a93c> { _try_acquire_console_sem + 0x4c }
Source : <0x0001a902> { _try_acquire_console_sem + 0x12 } IF !CC
JUMP pcrel
Stack info:
SP: [0x0202bd4c] <0x0202bd4c> /* kernel dynamic memory (maybe user-space) */
FP: (0x0202bd84)
Memory from 0x0202bd40 to 0202c000
0202bd40: 00000000 0202bd4c 0011ad50 [00948e14] 0202bd6c 0000c9fe
009cf114 00000000
0202bd60: 00000100 00000000 0000001f 0202bd84 0000ce16 cccccccd
<0001f4d6> 0202bdac
0202bd80: 0001f51a (0202bdac)<0003d818> 02008ae0 001842a4 00000046
00000000 00000000
0202bda0: 0000000a 00000000 00948e14 (0202bdd4) 0003f0e2 0018e260
00000046 00000000
0202bdc0: fffedc22 00000ccc 0001f7ac 00000ccc 0000000a
(0202bdf0)<000048fe> 00949408
0202bde0: 00000046 001898f8 00000001 00000001 (0202be20) 0000bb28
ffc00014 001898f4
0202be00: 00000001 00182454 00000000 0000b518 0011ad10 00000000
80000000 0000d2ee
0202be20:(00000000) 0000b518 00000000 00000000 00000000 00117e28
00008090 00000026
0202be40: 00000000 00000000 00000000 00117e28 00117e3a 00000007
00003024 000015ea
0202be60: 00117e28 000015ea 00117e28 00000000 000015b0 00000000
00000000 00000000
0202be80: 00000000 00000000 00000000 00000000 00000000 00000000
00000000 00000000
0202bea0: 00000000 00000000 00000000 00000000 0202ed60 00000000
00000000 0014fa1c
0202bec0: 0202bf30 00000000 0202bf1c 0018ba3c 001898f4 00000000
0000e7f1 00182454
0202bee0: 00182440 00000001 00182454 fffedc22 00000ccc 00000002
0000ffff 00182440
0202bf00: 0000e7f1 0000e7f1 00182440 00000006 00000000 0203a340
0000001f 0202bf4c
0202bf20: 00117c42 0017d26c 001898f8 001b04a0 00000001 00000001
00000001 00182454
0202bf40: 00000001 0017db34 0202bf74 0202bf74 001184d0 00000000
00000000 0000001f
0202bf60: 0011a240 00000000 ffffffff 0202bf70 0000000c 0202bf9c
00118598 00182454
0202bf80: 00000001 00000003 0000001f 00182458 0014f9d8 00000000
0202bfb4 0202bfb4
0202bfa0: 0019a32e 00000001 00000000 0202a000 00000000 0202bfe4
0019a6aa 00000000
0202bfc0: 00000000 00000000 0202a000 00000000 00000000 00000000
00000000 00000000
0202bfe0: 00000000 00000000 <000015b6> 00000000 00000000 00000000
ffffffff 00000006
Return addresses in stack:
address : <0x0001f4d6> { ___do_softirq + 0xce }
frame 1 : <0x0003d818> { _handle_IRQ_event + 0x50 }
frame 3 : <0x000048fe> { _asm_do_IRQ + 0x82 }
address : <0x000015b6> { _kernel_thread_helper + 0x6 }
On Mon, Sep 6, 2010 at 11:41 AM, real mz <[email protected]> wrote:
> Hi Mike,
> I had tried put the coreb_trampoline_start code at the beginning of
> the .l1.text before
> applied this "0x200 offset", but sometimes unexpected fault will assert.
>
> Index: arch/blackfin/kernel/setup.c
> ===================================================================
> --- arch/blackfin/kernel/setup.c (revision 9120)
> +++ arch/blackfin/kernel/setup.c (working copy)
> @@ -230,6 +230,8 @@
> unsigned long data_l1_len = (unsigned long)_data_l1_len;
> unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
>
> + blackfin_dma_early_init();
> +
> /* if necessary, copy L1 text to L1 instruction SRAM */
> if (L1_CODE_LENGTH && text_l1_len)
> early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma,
> @@ -245,6 +247,7 @@
> early_dma_memcpy((void *)COREB_L1_DATA_B_START, _data_b_l1_lma,
> data_b_l1_len);
>
> + early_dma_memcpy_done();
> #if ANOMALY_05000491
> blackfin_iflush_l1_entry[1] = (unsigned
> long)blackfin_icache_flush_range_l1 -
> (unsigned long)_stext_l1 + COREB_L1_CODE_START;
> Index: arch/blackfin/kernel/vmlinux.lds.S
> ===================================================================
> --- arch/blackfin/kernel/vmlinux.lds.S (revision 9120)
> +++ arch/blackfin/kernel/vmlinux.lds.S (working copy)
> @@ -176,6 +176,9 @@
> {
> . = ALIGN(4);
> __stext_l1 = .;
> +#ifdef CONFIG_SMP
> + *(.l1.text.secondary)
> +#endif
> *(.l1.text)
> #ifdef CONFIG_SCHEDULE_L1
> SCHED_TEXT
> Index: arch/blackfin/mach-bf561/secondary.S
> ===================================================================
> --- arch/blackfin/mach-bf561/secondary.S (revision 9120)
> +++ arch/blackfin/mach-bf561/secondary.S (working copy)
> @@ -13,7 +13,7 @@
> #include <asm/asm-offsets.h>
> #include <asm/trace.h>
>
> -__INIT
> +.section .l1.text.secondary
>
> /* Lay the initial stack into the L1 scratch area of Core B */
> #define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
>
>
>
> On Fri, Sep 3, 2010 at 11:17 PM, Mike Frysinger <[email protected]> wrote:
>> On Fri, Sep 3, 2010 at 06:05, <[email protected]> wrote:
>>> Revision 9122 Author steven.miao Date 2010-09-03 06:04:58 -0400 (Fri, 03 Sep
>>> 2010)
>>>
>>> Log Message
>>>
>>> [#6190] bf561 smp: fix sleep mode can not wake up by uart
>>>
>>> Add offset to avoid .l1.text section relocation overwrite coreb start
>>> entry. After coreb wakeup by IPI, it will execute coreb_trampoline_start
>>> entry at coreb l1 code area, but l1 iflush patch for ANOMALY_05000491
>>> overwrite the coreb_trampoline_start code area, so wakeup fail.
>>>
>>> Diff
>>>
>>> Modified: trunk/arch/blackfin/kernel/setup.c (9121 => 9122)
>>>
>>> /* if necessary, copy L1 text to L1 instruction SRAM */
>>> if (L1_CODE_LENGTH && text_l1_len)
>>> - early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma,
>>> + early_dma_memcpy((void *)COREB_L1_CODE_START + 0x200,
>>> _text_l1_lma,
>>> text_l1_len);
>>>
>>> /* if necessary, copy L1 data to L1 data bank A SRAM */
>>> @@ -247,7 +247,7 @@
>>>
>>> #if ANOMALY_05000491
>>> blackfin_iflush_l1_entry[1] = (unsigned
>>> long)blackfin_icache_flush_range_l1 -
>>> - (unsigned long)_stext_l1 + COREB_L1_CODE_START;
>>> + (unsigned long)_stext_l1 + COREB_L1_CODE_START +
>>> 0x200;
>>> #endif
>>
>> adding magic constants like 0x200 isnt going to fly. if the space is
>> reserved for the trampoline stuff, then place it into L1 sanely by
>> using .l1.text section markings.
>> -mike
>>
>
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