On Thursday 18 February 2016 16:58:54 Thomas Petazzoni wrote: > +- marvell,spi-base : List of GIC base SPI interrupts, one for each > + ODMI frame. Those SPI interrupts are 0-based, > + i.e marvell,spi-base = <128> will use SPI #96. > + See > Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt > + for details about the GIC Device Tree binding. >
Why are these not just in an 'interrupts' property as we do for other
nested irqchips?
Arnd
