On Mon, Feb 22, 2016 at 04:02:09PM -0800, Florian Fainelli wrote:
> On 22/02/16 10:09, Paul Burton wrote:
> > Index-based cache operations may be arbitrarily reordered by out of
> > order CPUs. Thus code which writes back the dcache & then invalidates
> > the icache using indexed cache ops must include a barrier between
> > operating on the 2 caches in order to prevent the scenario in which:
> >
> > - icache invalidation occurs.
> >
> > - icache fetch occurs, due to speculation.
> >
> > - dcache writeback occurs.
> >
> > If the above were allowed to happen then the icache would contain stale
> > data. Forcing the dcache writeback to complete before the icache
> > invalidation avoids this.
>
> Is that also true for CPUs with have cpu_has_ic_fills_dc?
Hi Florian,
Good question. I imagine not, but probably need to think some more & ask
some questions.
Thanks,
Paul
