From: Borislav Petkov <[email protected]> So Andy had a good idea about using a cacheline-aligned, seldomly used per-cpu var as the MONITORX target but we can't use it in preemptible context. The first simple idea I have is to disable preemption around us dereffing it.
Better ideas? Signed-off-by: Borislav Petkov <[email protected]> Cc: Andy Lutomirski <[email protected]> Cc: Huang Rui <[email protected]> Cc: [email protected] --- arch/x86/lib/delay.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/x86/lib/delay.c b/arch/x86/lib/delay.c index e912b2f6d36e..c1810afcd2ea 100644 --- a/arch/x86/lib/delay.c +++ b/arch/x86/lib/delay.c @@ -92,17 +92,22 @@ static void delay_tsc(unsigned long __loops) static void delay_mwaitx(unsigned long __loops) { u64 start, end, delay, loops = __loops; + struct tss_struct *t; + + /* + * Use cpu_tss as a cacheline-aligned, seldomly accessed per-cpu + * variable as the monitor target. + */ + preempt_disable(); + t = this_cpu_ptr(&cpu_tss); + preempt_enable(); start = rdtsc_ordered(); for (;;) { delay = min_t(u64, MWAITX_MAX_LOOPS, loops); - /* - * Use cpu_tss as a cacheline-aligned, seldomly - * accessed per-cpu variable as the monitor target. - */ - __monitorx(this_cpu_ptr(&cpu_tss), 0, 0); + __monitorx(t, 0, 0); /* * AMD, like Intel, supports the EAX hint and EAX=0xf -- 2.3.5
