On Tue, Jun 14, 2016 at 7:46 AM, Yakir Yang <[email protected]> wrote: > There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced > by commit bcec20fd5ad6 ("drm: bridge: analogix/dp: add some rk3288 special > registers setting"). > > The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1 > BIT 0, not BIT 1. > > Signed-off-by: Yakir Yang <[email protected]> > Reviewed-by: Tomasz Figa <[email protected]> > Tested-by: Javier Martinez Canillas <[email protected]>
Reviewed-by: Sean Paul <[email protected]> > --- > Changes in v3: > - Add reviewed flag from Tomasz. > [https://chromium-review.googlesource.com/#/c/346315/15] > - Add tested flag from Javier > > Changes in v2: None > > drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > index 337912b..88d56ad 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > @@ -163,8 +163,8 @@ > #define HSYNC_POLARITY_CFG (0x1 << 0) > > /* ANALOGIX_DP_PLL_REG_1 */ > -#define REF_CLK_24M (0x1 << 1) > -#define REF_CLK_27M (0x0 << 1) > +#define REF_CLK_24M (0x1 << 0) > +#define REF_CLK_27M (0x0 << 0) > > /* ANALOGIX_DP_LANE_MAP */ > #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) > -- > 1.9.1 > > > _______________________________________________ > dri-devel mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/dri-devel
