From: Zhangfei Gao <[email protected]>

Adds clk support for the pl031 RTC on hi6220

Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Wei Xu <[email protected]>
Cc: Guodong Xu <[email protected]>
Signed-off-by: Zhangfei Gao <[email protected]>
[jstultz: Forward ported, tweaked commit description]
Signed-off-by: John Stultz <[email protected]>
---
v3: No changes from v1, version noted just to be consistent
    with the other patch in this patchset.

 drivers/clk/hisilicon/clk-hi6220.c       | 2 ++
 include/dt-bindings/clock/hi6220-clock.h | 5 +++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/hisilicon/clk-hi6220.c 
b/drivers/clk/hisilicon/clk-hi6220.c
index f02cb41..76de9a7 100644
--- a/drivers/clk/hisilicon/clk-hi6220.c
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -68,6 +68,8 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] 
__initdata = {
        { HI6220_TIMER7_PCLK, "timer7_pclk", "clk_tcxo", 
CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 22, 0, },
        { HI6220_TIMER8_PCLK, "timer8_pclk", "clk_tcxo", 
CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 23, 0, },
        { HI6220_UART0_PCLK,  "uart0_pclk",  "clk_tcxo", 
CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 24, 0, },
+       { HI6220_RTC0_PCLK,   "rtc0_pclk",   "clk_tcxo", 
CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 25, 0, },
+       { HI6220_RTC1_PCLK,   "rtc1_pclk",   "clk_tcxo", 
CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 26, 0, },
 };
 
 static void __init hi6220_clk_ao_init(struct device_node *np)
diff --git a/include/dt-bindings/clock/hi6220-clock.h 
b/include/dt-bindings/clock/hi6220-clock.h
index 70ee383..6b03c84 100644
--- a/include/dt-bindings/clock/hi6220-clock.h
+++ b/include/dt-bindings/clock/hi6220-clock.h
@@ -55,8 +55,9 @@
 #define HI6220_TIMER7_PCLK     34
 #define HI6220_TIMER8_PCLK     35
 #define HI6220_UART0_PCLK      36
-
-#define HI6220_AO_NR_CLKS      37
+#define HI6220_RTC0_PCLK       37
+#define HI6220_RTC1_PCLK       38
+#define HI6220_AO_NR_CLKS      39
 
 /* clk in Hi6220 systrl */
 /* gate clock */
-- 
1.9.1

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