On Fri, Aug 19, 2016 at 04:44:53PM +0200, Borislav Petkov wrote: > On Fri, Aug 19, 2016 at 03:34:22PM +0200, Peter Zijlstra wrote: > > Can't those events are NB events and cannot be used on per CPU counters. > > It fugures, considering L3 is part of the NB on AMD. > > So the Intel ones are special in the sense that they can be used on per > CPU counters even though they're not really per-CPU?
Intel has L3 (and L2,1) request and miss events per logical CPU. The CPU still issues the load/store that causes the request and miss and thus can be accounted to the program under execution. Intel also has a bunch of L3 events at the uncore of course.
