On 10/01/16 12:24, Sekhar Nori wrote: >> That's good to hear, but I think the priorities should be set: >> LCDC and EDMA30TC1 to highest priority >> EDMA30TC0 to priority 2 >> >> The 0TC0 is used by MMC and if you want to play a video you might need the >> servicing TC to be higher priority then other masters. >> >> If audio playback would trigger sync losts in lcdc then we might need to move >> 0TC1 to priority 1. >> >> I agree that LCDC priority needs to be higher, but I do wonder why the >> default >> (5) is not working and if it is not working why it is 5... >> >> My guess is that the change in the PBBPR register is the one actually helping >> here. > > Good point, Peter. If you are booting off NFS and not playing any audio, > then there is pretty much no EDMA generated traffic on the interconnect.
Yes, this is my understanding as well. > I would guess too that its the PBBPR setting that is making a > difference. The EDMA vs LCDC priority adjustment might be needed in > particular situations too, but specific experiments should be done to > narrow down on that being the cause. True, we can use some conservative values for the priority, but the PBBPR register for sure needs to be updated. > In any case, to configure the PBBR, you will have to introduce a driver > for it in drivers/memory. Then you can set it up per board using a DT > parameter. and we can reuse the introduced bindings for am335x and OMAP1/2 as well. On OMAP the legacy DMA API provided a call to raise the priority of the sDMA in EMIF :o That needs to be removed and replaced. -- Péter
