On Thursday 13 October 2016 03:37 PM, Peter Ujfalusi wrote:
> On 10/10/16 17:12, Peter Ujfalusi wrote:
>> On 10/10/16 15:07, Vignesh R wrote:
>>> From: Sebastian Andrzej Siewior <bige...@linutronix.de>
>>> This DMA driver is used by 8250-omap on DRA7-evm. There is one
>>> requirement that is to pause a transfer. This is currently used on the RX
>>> side. It is possible that the UART HW aborted the RX (UART's RX-timeout)
>>> but the DMA controller starts the transfer shortly after.
>>> Before we can manually purge the FIFO we need to pause the transfer,
>>> check how many bytes it already received and terminate the transfer
>>> without it making any progress.
>>> From testing on the TX side it seems that it is possible that we invoke
>>> pause once the transfer has completed which is indicated by the missing
>>> CCR_ENABLE bit but before the interrupt has been noticed. In that case the
>>> interrupt will come even after disabling it.
>>> The AM572x manual says that we have to wait for the CCR_RD_ACTIVE &
>>> CCR_WR_ACTIVE bits to be gone before programming it again here is the
>>> drain loop. Also it looks like without the drain the TX-transfer makes
>>> sometimes progress.
>>> One note: The pause + resume combo is broken because after resume the
>>> the complete transfer will be programmed again. That means the already
>>> transferred bytes (until the pause event) will be sent again. This is
>>> currently not important for my UART user because it does only pause +
>> Acked-by: Peter Ujfalusi <peter.ujfal...@ti.com>
> Can you resend the patch with corrected subject line?
> dmaengine: omap-dma: ....
Sent v4 in reply to the patch fixing up the subject. Thanks!