On Mon, Oct 17, 2016 at 09:43:41AM -0700, Yu, Fenghua wrote:
> > > > I wonder whether this is the proper abstraction level. We might as
> > > > well do the following:
> > > >
> > > > rdtresources[] = {
> > > > {
> > > > .name = "L3",
> > > > },
> > > > {
> > > > .name = "L3Data",
> > > > },
> > > > {
> > > > .name = "L3Code",
> > > > },
> > > >
> > > > and enable either L3 or L3Data+L3Code. Not sure if that makes things
> > > > simpler, but it's definitely worth a thought or two.
> > >
> > > This way will be better than having cdp_enabled/capable for L3 and not
> > > for L2. And this doesn't change current userinterface design either,
> > > I think.
> >
> > User interface would change if you did this. The schemata file would look
> > like
> > this with CDP enabled:
> >
> > # cat schemata
> > L3Data:0=fffff;1=fffff;2=fffff;3=fffff
> > L3Code:0=fffff;1=fffff;2=fffff;3=fffff
> >
> > but that is easier to read than the current:
> >
> > # cat schemata
> > L3:0=fffff,fffff;1=fffff,fffff;2=fffff,fffff;3=fffff,fffff
> >
> > which gives you no clue on which mask is code and which is data.
>
> Right.
>
> Also changing to uniform format <resname>:<id1>=cbm1;<id2>=cbm2;...
> is lot easier to parse schemata line in CDP mode.
>
> So I'll change the code and doc to have two new resources: L3Data and L3Code
> for CDP mode.
Doc change (fold into part 05):
diff --git a/Documentation/x86/intel_rdt_ui.txt
b/Documentation/x86/intel_rdt_ui.txt
index e56781952f42..b9f634c9a058 100644
--- a/Documentation/x86/intel_rdt_ui.txt
+++ b/Documentation/x86/intel_rdt_ui.txt
@@ -97,13 +97,18 @@ With CDP disabled the L3 schemata format is:
L3 details (CDP enabled via mount option to resctrl)
----------------------------------------------------
-When CDP is enabled, you need to specify separate cache bit masks for
-code and data access. The generic format is:
+When CDP is enabled L3 control is split into two separate resources
+so you can specify independent masks for code and data like this:
- L3:<cache_id0>=<d_cbm>,<i_cbm>;<cache_id1>=<d_cbm>,<i_cbm>;...
+ L3data:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
+ L3code:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
-where the d_cbm masks are for data access, and the i_cbm masks for code.
+L2 details
+----------
+L2 cache does not support code and data prioritization, so the
+schemata format is always:
+ L2:<cache_id0>=<cbm>;<cache_id1>=<cbm>;...
Example 1
---------
