On Mon, Nov 28, 2016 at 05:03:37PM -0600, Grygorii Strashko wrote: > The CPTS drivers uses 8sec period for overflow checking with > assumption that CPTS retclk will not exceed 500MHz. But that's not > true on some TI platforms (Kesytone 2). As result, it is possible that > CPTS counter will overflow more than once between two readings. > > Hence, fix it by selecting overflow check period dynamically as > max_sec_before_overflow/2, where > max_sec_before_overflow = max_counter_val / rftclk_freq. > > Cc: John Stultz <john.stu...@linaro.org> > Cc: Thomas Gleixner <t...@linutronix.de> > Signed-off-by: Grygorii Strashko <grygorii.stras...@ti.com>
Acked-by: Richard Cochran <richardcoch...@gmail.com>
