On Wed, Nov 30, 2016 at 09:04:41PM -0000, Thomas Gleixner wrote: > It's remarkable that the test program provided by David triggers on ARM64 > and MIPS64 really quick, but it refuses to reproduce on x8664, while the > problem exists there as well. That refusal might explain that this got not > discovered earlier despite the bug existing from day one of the rtmutex > implementation more than 10 years ago.
> - clear_rt_mutex_waiters(lock); So that compiles into: andq $0xfffffffffffffffe,0x48(%rbx) With is a RmW memop. Now per the architecture documents we can decompose that into a normal load-store and the race exists. But I would not be surprised if that starts with the cacheline in exclusive mode (because it knows it will do the store). Which makes it a very tiny race indeed.