On Tue, 21 Feb 2017 13:02:48 +0100 Marc Gonzalez <[email protected]> wrote:
> On 21/02/2017 12:06, Boris Brezillon wrote: > > > Marc Gonzalez wrote: > > > >> On 20/02/2017 22:12, Boris Brezillon wrote: > >> > >>> Some NAND controllers can assign different NAND timings to different > >>> CS lines. Pass the CS line information to ->setup_data_interface() so > >>> that the NAND controller driver knows which CS line is concerned by > >>> the setup_data_interface() request. > >> > >> I'm confused, because I thought I was already doing that. > >> On my platform, I have different timings for each chip. > >> (thus, for each CS, right?) > >> > >> In chip->select_chip, I program the appropriate timings > >> which the controller will be using. > >> > >> What am I missing? > > > > Maybe you don't have multi-dies chips, which is the case I'm fixing > > here. If you have 2 separate chips, the existing hook should work just > > fine. > > Right. You asked me to add an explicit: > > res = of_property_count_u32_elems(np, "reg"); > if (res < 0) > return res; > > if (res != 1) > return -ENOTSUPP; /* Multi-CS chips are not supported */ > > I was under the impression that multi-die chips are seen as a single > larger "composite" chip. And I had assumed that different dies would > not only require identical timings, but would also be identical in > all other aspects. This it incorrect? This is correct, except some chips (that's true at least for ONFI compatible ones) allow dynamic configuration of timings, and each die can be configured in a different timing mode. That's what's happening when you reset dies. They will automatically enter timing mode 0 (the slowest mode), and you have to explicitly set them back to timing mode X (the fastest supported mode). While doing that, you'll have some of your dies configured in timing 0, while others have already been switched to timing mode X, and that's the main reason for having per-die timing configuration.
