From: Gabriel Fernandez <[email protected]> This patch-set contains 2 fixes. One concerning exclusion of wrong values for PLLQ (0 & 1) And the second is a fix about timeout management of PLL and LSE/LSI clocks.
Gabriel Fernandez (2): clk: stm32f4: fix: exclude values 0 and 1 for PLLQ clk: stm32f4: fix timeout management for pll and ready gate drivers/clk/clk-stm32f4.c | 56 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 39 insertions(+), 17 deletions(-) -- 1.9.1
