On Sat, May 27, 2017 at 07:08:34PM +0300, Andy Shevchenko wrote:
> On Fri, May 26, 2017 at 7:09 PM, Mika Westerberg
> <mika.westerb...@linux.intel.com> wrote:
> > The DMA (NHI) port of a switch provides access to the NVM of the host
> > controller (and devices starting from Intel Alpine Ridge). The NVM
> > contains also more complete DROM for the root switch including vendor
> > and device identification strings.
>
> > + ret = dma_port_flash_read_block(dma, address, dma->buf,
> > + ALIGN(nbytes, 4));
> > + if (ret) {
> > + if (ret == -ETIMEDOUT) {
> > + if (retries--)
> > + continue;
> > + ret = -EIO;
> > + }
> > + return ret;
> > + }
> > +
> > + memcpy(buf, dma->buf + offset, nbytes);
>
> > + do {
> > + u32 nbytes = min_t(u32, size, MAIL_DATA_DWORDS * 4);
> > + int ret;
> > +
> > + memcpy(dma->buf + offset, buf, nbytes);
> > +
> > + ret = dma_port_flash_write_block(dma, address, buf, nbytes);
> > + if (ret) {
> > + if (ret == -ETIMEDOUT) {
> > + if (retries--)
> > + continue;
> > + ret = -EIO;
> > + }
> > + return ret;
> > + }
>
> Just to be sure I didn't miss anything.
> Can't we just map buffer into DMA capable address space instead of
> memcpy()'ing?
The buffer is there to handle unaligned (non-dword) reads and writes. I
suppose you could do that but it adds more complexity than it is worth
IMHO because this is about sending and receiving messages over low-speed
control channel.
If there is a need to optimize things like this, I think we can do that
later on.
